Patent US5392441A successfully refreshed from Google Patents.
US5392441A
Expired / Lapsed
US
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Pump bus to avoid indeterminacy in reading variable bit field
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-10-26
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Granted: 1995-02-21
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Expires: 2013-10-26
Abstract
Abstract A data field having a variable number of zero-level bits is read by a bus in a digital system, wherein the bus is pumped by writing all logical "one" bits onto the bus lines just before they are read. The unused bits will then be still in a logical "one" state, i.e. a known value, rather than floating or at an indeterminate value. A program for performing this operation in a computer uses steps to prevent other operations such as refresh cycles or interrupts from being interposed between the write and read cycles. A CPU may use this method to read a system identifier value upon boot-up, for example.
Inventors
- 👤 Gary L. Brasher
- 👤 James H. Nuckols
- 👤 Jeffrey S. Watters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:59
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
314 words
A computer system having memory and data locations, comprising: a) a CPU with means for fetching and executing instructions from the memory and performing operations, the CPU including an address space; b) system bus means including an address bus and a data bus with capacitive effects, the system bus means being coupled to the memory and said CPU, wherein the data bus is comprised of a first number of data lines; c) a reference data location within said address space of the CPU and coupled to said system bus means; said reference data location storing a second number of data bit values identifying a configuration parameter of the computer system and driving only said second number of data bit values onto a second number of said first number of data lines of said data bus when said reference data location is read, said second number being less than said first number and said data lines other than said second number of data lines being undriven when said reference data location is read; d) and writing and immediately thereafter reading means coupled to said system bus means for writing to said first number of data lines of said data bus preselected data of known value and then immediately thereafter reading a first number of data bit values from said first number of data lines, said data bit values on said second number of data lines being provided by said reference data location and said data bit values on said data lines other than said second number of data lines being provided by said preselected data of known value previously written to said data lines other than said second number of data lines, said preselected data of known value having been retained on said data lines other than said second number of data lines during said reading due to said capacitive effects on said data bus.
Claim 2
Dependent Claim
314 words
A computer system having memory and data locations, comprising: a) a CPU with means for fetching and executing instructions from the memory and performing operations, the CPU including an address space; b) system bus means including an address bus and a data bus with capacitive effects, the system bus means being coupled to the memory and said CPU, wherein the data bus is comprised of a first number of data lines; c) a reference data location within said address space of the CPU and coupled to said system bus means; said reference data location storing a second number of data bit values identifying a configuration parameter of the computer system and driving only said second number of data bit values onto a second number of said first number of data lines of said data bus when said reference data location is read, said second number being less than said first number and said data lines other than said second number of data lines being undriven when said reference data location is read; d) and writing and immediately thereafter reading means coupled to said system bus means for writing to said first number of data lines of said data bus preselected data of known value and then immediately thereafter reading a first number of data bit values from said first number of data lines, said data bit values on said second number of data lines being provided by said reference data location and said data bit values on said data lines other than said second number of data lines being provided by said preselected data of known value previously written to said data lines other than said second number of data lines, said preselected data of known value having been retained on said data lines other than said second number of data lines during said reading due to said capacitive effects on said data bus.
Claim 3
Dependent Claim
62 words
A system according to claim 1, wherein a plurality of functions are performed in the computer system utilizing said system bus means and wherein said system includes means coupled to said system bus means for detecting when a preselected function is performed, said writing and immediately thereafter reading means writing said preselected data immediately after said detecting means detects said preselected function.
Claim 4
Dependent Claim
22 words
A system according to claim 2 wherein said preselected function is a refresh of the memory connected to said system bus means.
Claim 5
Dependent Claim
35 words
A system according to claim 1 wherein said second number of data bit values from said reference data location are set to logic zero values, and said preselected data of known value comprises logic-one values.
Claim 6
Dependent Claim
36 words
A system according to claim 4 wherein said logic-zero values are at a voltage of ground, and said logic-one values are at a positive voltage of about that used as a power supply for said CPU.
Claim 7
Dependent Claim
73 words
A system according to claim 1 wherein said reference data location is coupled to said data bus and includes a second number of locations for storing said second number of data bit values, the system further comprising: a second number of tri-state buffers associated with each of said second number of data bit values coupled between said data bit value locations in said reference data location and said second number of data lines.
Claim 8
Dependent Claim
177 words
A system according to claim 1 wherein said second number is less than eight, and said reference data location stores said second number of data bit values at variable locations within a byte mixed with unused bits of said byte, said writing and immediately thereafter reading means becoming operational and writing to said first number of data lines of said data bus preselected data of known value and then immediately thereafter reading a first number of data bit values from said first number of data lines, said data bit values on said second number of data lines being provided by said reference data location and said data bit values on said data lines other than said second number of data lines being provided by said preselected data of known value previously written to said data lines other than said second number of data lines, said preselected data of known value having been retained on said data lines other than said second number of data lines during said reading due to said capacitive effects on said data bus.
Claim 9
Independent Claim
196 words
A method of operating a digital system having a data bus with capacitive effects comprised of a first number of data lines, including the steps of: a) writing to the first number of data lines of the data bus of said system a preselected data value, wherein said step of writing drives the first number of data lines of the data bus to known logic values; b) immediately after writing said preselected value reading a first number of data bit values from a data location coupled to the data bus storing a second number of data bit values identifying a configuration parameter of the digital system, wherein said second number is less than a the first number; and c) the data location driving said second number of data bit values onto only a second number of the first number of data lines during said data location reading, the data lines not driven by said data location entering an undriven state and still retaining said preselected values during said data location reading due to the capacitive effects on the data bus and providing said retained preselected values during said reading a first number of data bit values.
Claim 10
Independent Claim
196 words
A method of operating a digital system having a data bus with capacitive effects comprised of a first number of data lines, including the steps of: a) writing to the first number of data lines of the data bus of said system a preselected data value, wherein said step of writing drives the first number of data lines of the data bus to known logic values; b) immediately after writing said preselected value reading a first number of data bit values from a data location coupled to the data bus storing a second number of data bit values identifying a configuration parameter of the digital system, wherein said second number is less than a the first number; and c) the data location driving said second number of data bit values onto only a second number of the first number of data lines during said data location reading, the data lines not driven by said data location entering an undriven state and still retaining said preselected values during said data location reading due to the capacitive effects on the data bus and providing said retained preselected values during said reading a first number of data bit values.
Claim 11
Dependent Claim
35 words
A method according to claim 8 wherein said digital system is a computer executing instructions, and said step of reading is performed by an instruction executed immediately after an instruction performing said step of writing.
Claim 12
Dependent Claim
23 words
A method according to claim 9, wherein execution of an instruction by said computer requires a plurality of machine cycles of said computer.
Claim 13
Dependent Claim
32 words
A method according to claim 8 wherein said preselected data value is a field of logic-one bits and wherein said second number of data bit values include logic-zero bits as intentional data.
Claim 14
Independent Claim
225 words
A method of identifying characteristics of a digital system having a data bus with capacitive effects comprised of a first number of data lines, and a CPU coupled to the data bus, including the steps of: a) storing a multiple-bit identifying code at a selected location coupled to the data bus addressable by the CPU in said system, wherein said multiple-bit identifying code identifies a configuration parameter of the digital system and wherein less than all of the bits at said location includes bits of said code; b) writing a preselected data value to the first number of data lines of the data bus of said system addressable at said location, wherein said step of writing drives said data lines to known logic values; c) immediately after writing said preselected value, reading a first number of data bit values from said selected location to detect said identifying code; and d) said data location driving said identifying code onto a number of the first number of data lines less than said first number during said read operation, the data lines not driven by said data location entering an undriven state and still retaining said preselected values during said data location reading due to the capacitive effects on the data bus and providing said retained preselected values during said reading a first number of data bit values.
Claim 15
Independent Claim
225 words
A method of identifying characteristics of a digital system having a data bus with capacitive effects comprised of a first number of data lines, and a CPU coupled to the data bus, including the steps of: a) storing a multiple-bit identifying code at a selected location coupled to the data bus addressable by the CPU in said system, wherein said multiple-bit identifying code identifies a configuration parameter of the digital system and wherein less than all of the bits at said location includes bits of said code; b) writing a preselected data value to the first number of data lines of the data bus of said system addressable at said location, wherein said step of writing drives said data lines to known logic values; c) immediately after writing said preselected value, reading a first number of data bit values from said selected location to detect said identifying code; and d) said data location driving said identifying code onto a number of the first number of data lines less than said first number during said read operation, the data lines not driven by said data location entering an undriven state and still retaining said preselected values during said data location reading due to the capacitive effects on the data bus and providing said retained preselected values during said reading a first number of data bit values.
Claim 16
Dependent Claim
38 words
A method according to claim 12 wherein said digital system is a computer executing instructions via said CPU, and said step of reading is performed by an instruction executed immediately after an instruction performing said step of writing.
Claim 17
Dependent Claim
28 words
A method according to claim 12 wherein said preselected data value is a field of logic-one bits and wherein said identifying code includes logic-zero bits as intentional data.
Claim 18
Dependent Claim
22 words
A method according to claim 14 including the step of disabling interrupts of said CPU just prior to said step of writing.
Claim 19
Dependent Claim
39 words
A method according to claim 15, wherein the CPU executes refresh operations for dynamic memory coupled to the data bus; and wherein said step of writing is performed after said CPU has just executed one of said refresh operations.
Claim 20
Dependent Claim
71 words
A method according to claim 12 wherein said digital system is a computer executing instructions via said CPU, with each instruction requiring at least one machine cycle of said CPU, and said step of reading is performed by a first instruction executed immediately after a given instruction performing said step of writing, each of said first instruction and said given instruction requiring more than one said machine cycle of said computer.
Claim 21
Dependent Claim
28 words
A system according to claim 1, wherein said writing and immediately thereafter reading means writes said preselected data of known value to said first number of data lines.
Claim 22
Dependent Claim
24 words
A method according to claim 8, wherein said step of writing includes writing said preselected data value to the first number of data lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |