EP0175526A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data bus discharging circuit
Assignee: Oki Electric Industry Co Ltd
•
Filing: 1985-09-06
•
Granted: —
•
Expires: 2005-09-06
Abstract
Abstract 57 A data bus discharging circuit capable of enabling the high-speed operation of a microprocessor, comprising a control signal generating circuit which provides control signals, a precharge/enable signal generating circuits which provides a precharge control signal and an enable signal, a discharge detecting circuit which detects the potential of the bit lines of the data bus, and a discharging circuit which sets the bit lines of the data bus selectively at the ground potential.
Inventors
- 👤 Hiroshi Oki Electric Ind. Co. Ltd. Yokouchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 07:02
CPC Classifications
G; G06; G06F; G06F1/00; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
188 words
A data bus discharging circuit comprising: (a) a control signal generating circuit which provides a control signal of one logic level, when all the bit lines of a data bus become the one logic level, and provides a control signal of an inverse logic level, when a clock signal is given thereto; (b) a precharge/enable signal generating circuit which generates a precharge control signal to charge the data bus, when said control signal is the inverse logic level, and provides an enable signal to actuate an internal gate circuit, when said control signal is the one logic level; (c) discharge detection circuits each of which is connected to the bit line of said data bus, provides a discharge control signal, when the potential of the bit line is below a predetermined level, and is reset when the control signal of said control signal generating circuit is the inverse logic level; and (d) discharging means which is connected to the bit lines of said data bus, and makes the potential of the bit lines drop to the ground potential when said discharge detecting circuit provides a discharge control signal.
Claim 2
Dependent Claim
188 words
A data bus discharging circuit comprising: (a) a control signal generating circuit which provides a control signal of one logic level, when all the bit lines of a data bus become the one logic level, and provides a control signal of an inverse logic level, when a clock signal is given thereto; (b) a precharge/enable signal generating circuit which generates a precharge control signal to charge the data bus, when said control signal is the inverse logic level, and provides an enable signal to actuate an internal gate circuit, when said control signal is the one logic level; (c) discharge detection circuits each of which is connected to the bit line of said data bus, provides a discharge control signal, when the potential of the bit line is below a predetermined level, and is reset when the control signal of said control signal generating circuit is the inverse logic level; and (d) discharging means which is connected to the bit lines of said data bus, and makes the potential of the bit lines drop to the ground potential when said discharge detecting circuit provides a discharge control signal.
Claim 3
Dependent Claim
20 words
A data bus discharging circuit according to Claim 1, wherein said control signal generating circuit is a flip flop circuit.
Claim 4
Dependent Claim
53 words
A data bus discharging circuit according to Claim 1, wherein said precharge/enable signal generating circuit comprises: (a) a precharge control signal generating circuit which provides said precharge control signal; (b) an enable signal generating circuit which generates said enable signal; and (c) a delaying circuit which delays the transfer of said enable signal.
Claim 5
Dependent Claim
23 words
A data bus discharging circuit according to claim 3, wherein said precharge control signal generating circuit comprises a NOR circuit and an inverter.
Claim 6
Dependent Claim
23 words
A data bus discharging circuit according to claim 3, wherein said enable signal generating circit comprises an AND circuit and a buffer circuit.
Claim 7
Dependent Claim
18 words
A data bus discharging circuit according to claim 3, wherein said delay circuit comprises a plurality of inverters.
Claim 8
Dependent Claim
102 words
A data bus initialising circuit, comprising: (a) initialising means (80) for applying to data lines of a data bus (190) a common predetermined logic signal level (VD D ), and (b) means (140, 160) for thereafter applying data signals of first and second different logic levels (VDD, OV) selectively to the data lines characterised by (c) control means (210, 260) for selectively applying to the or each said data line which receives a said data signals of said second logic level, an additional control potential (O V ) for causing the level of the line to move towards said second signal level.
Claim 9
Dependent Claim
102 words
A data bus initialising circuit, comprising: (a) initialising means (80) for applying to data lines of a data bus (190) a common predetermined logic signal level (VD D ), and (b) means (140, 160) for thereafter applying data signals of first and second different logic levels (VDD, OV) selectively to the data lines characterised by (c) control means (210, 260) for selectively applying to the or each said data line which receives a said data signals of said second logic level, an additional control potential (O V ) for causing the level of the line to move towards said second signal level.
Claim 10
Dependent Claim
82 words
A circuit according to claim 7 wherein said control means comprises: detection circuit means (210) for each of said data lines and arranged to produce an output signal (OUT) in response to a particular data line signal level moving towards said second signal level upon said data signals being applied to the data bus (190), and means (260, 261) responsive to the occurrence of said output signal (OUT) for applying said additional control potential (O V ) to said particular data line.
Claim 11
Dependent Claim
59 words
A circuit according to claim 7 or 8 including initialisation completion detection means (90) operative to detemine when said lines have been set to said common logic level by said initialisation means (80) and to provide a control signal (L) indicative thereof, and means (280) responsive to said control signal (L) to disable operation of the initialising means (80).
Claim 12
Dependent Claim
41 words
A circuit according to claim 7, 8 or 9 including data register means (140, 160) arranged to store data from the bus (190) during operation of said initialising means (80) and to apply the stored data to the bus (190) thereafter.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.