Patent US2009056A successfully refreshed from Google Patents.
EP0082980A1
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Signal transfer arrangement using a bus as a storage device
Assignee: International Business Machines Corp
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Filing: 1982-12-02
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Granted: —
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Expires: 2002-12-02
Abstract
Abstract The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
Inventors
- 👤 Virgil Dean Wyatt
- 👤 Wayne Richard Kraft
- 👤 Nandor Gyorgy Thoma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
201 words
In a large scale integration data processor (10) formed on an integrated circuit chip, a signal transfer mechanism comprising : a plural-bit bus (16) formed on said integrated circuit chip for transferring plural-bit binary sgnals between different locations on the chip, plural-bit signal source means (17, 18, 19, 26, 32, 35) formed on said integrated circuit chip and coupled to said plural-bit bus .for supplying plural-bit binary signals thereto, and plural-bit signal destination means (17, 18, 19, 26, 31, 32, 35) formed on said integrated circuit chip and coupled to said plural-bit bus for receiving plural-bit binary signals therefrom; said signal transfer mechanism being characterized in that it comprises processor control unit (14) coupled to said signal source and signal destination means for enabling a first one of said signal source means to put a plural-bit binary signal onto said plural-bit bus during a first time interval and for enabling a first one of said signal destination means to take in this plural-bit binary signal from said plural-bit bus during a second and different time interval, the inherent capacitance of said plural-bit bus serving to store the plural-bit binary signal during the first and second and any intervening time intervals. :
Claim 2
Dependent Claim
201 words
In a large scale integration data processor (10) formed on an integrated circuit chip, a signal transfer mechanism comprising : a plural-bit bus (16) formed on said integrated circuit chip for transferring plural-bit binary sgnals between different locations on the chip, plural-bit signal source means (17, 18, 19, 26, 32, 35) formed on said integrated circuit chip and coupled to said plural-bit bus .for supplying plural-bit binary signals thereto, and plural-bit signal destination means (17, 18, 19, 26, 31, 32, 35) formed on said integrated circuit chip and coupled to said plural-bit bus for receiving plural-bit binary signals therefrom; said signal transfer mechanism being characterized in that it comprises processor control unit (14) coupled to said signal source and signal destination means for enabling a first one of said signal source means to put a plural-bit binary signal onto said plural-bit bus during a first time interval and for enabling a first one of said signal destination means to take in this plural-bit binary signal from said plural-bit bus during a second and different time interval, the inherent capacitance of said plural-bit bus serving to store the plural-bit binary signal during the first and second and any intervening time intervals. :
Claim 3
Dependent Claim
90 words
A signal transfer mechanism in accordance with claim 1 wherein said processor control unit (14) enables a second one of said signal destination means (17, 18, 19, 26, 31, 32, 35) to take in the same plural-bit binary signal as was taken in by said first one of signal destination means during the second time interval, from said plural-bit bus (16) during a third time interval, the inherent capacitance of said plural-bit bus serving to store the plural-bit binary signal during the second and third and any intervening time intervals.
Claim 4
Dependent Claim
25 words
A signal transfer mechanism in accordance with claim 1 or 2 wherein said first and second time intervals are first and second processor control cycles.
Claim 5
Dependent Claim
91 words
A signal transfer mechanism in accordance with any one of claim 1, 2 or 3 wherein each of said signal source means (17, 18, 19, 26, 32, 35) is a plural-stage binary register having output circuits (90) coupling different register stages to different ones of the bit lines of said plural-bit bus (16) and each of said signal destination means (17, 18, 19, 26, 31, 32, 35) is a plural-stage binary register having input circuits (75) coupling different register stages to different ones of the bit lines of said plural-bit bus.
Claim 6
Dependent Claim
96 words
A signal transfer mechanism in accordance with any one of claims 1 to 4 wherein two of said signal source and destination means are registers (18, 19) associated with a plural-bit arithmetic and logic unit (20) having output gates (21) for coupling different arithmetic and logic unit output lines to different ones of the bit lines of said plural-bit bus (16) and wherein said processor control unit (14) is coupled to said output gates for enabling said arithmetic and logic unit to put its plural-bit output signal onto said plural-bit bus during said first time interval.
Claim 7
Dependent Claim
181 words
A signal transfer mechanism in accordance with any one of the preceding claims wherein said processor control unit (14) includes : a microword control storage mechanism for producing a sequence of microwords for controlling the execution of a processor instruction; a control circuit (40, 41) responsive one at a time to the microwords from the control storage mechanism for producing for each microword a plurality of control point signals for controlling the operation of the data processor for one microword cycle, some of said control point signals (Gl, G2) being produced during a first microword cycle for enabling one of said signal source means (17, 18, 19, 26, 32, 35) to put its plural-bit binary signal onto said plural-bit bus (16) during this first microword cycle, and some of said control point signals (L1, L2) being produced during a second and different microword cycle for enabling one of said signal destination means (17, 18, 19, 26, 31, 32, 35) to take in during this second microword cycle the plural-bit binary signal put out by said one of the signal source means.
Claim 8
Dependent Claim
82 words
A signal transfer mechanism according to any one of the preceding claims comprising a precharge/discharge mechanism formed on the integrated circuit chip and coupled to said plural-conductor bus (16) and including programmable precharge circuitry for charging none, one, some or all of the bus conductors to a predetermined voltage level representing the first binary value and further including programmable discharge circuitry for discharging none, one, some or all of the bus conductors to a predetermined voltage level representing the second binary value.
Claim 9
Dependent Claim
78 words
A signal transfer mechanism according to claim7 wherein said processor control unit (14) is coupled to said precharge/discharge mechanism (27) for causing said precharge circuitry to charge each of the conductors of said bus (16) during a first time interval and for enabling one of said signal source means (17, 18, 19, 26, 32, 35) to discharge the appropriate bus conductors during a second and different time interval for producing on the bus a desired plural-bit binary signal.
References Cited (Backward Citations)
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