Self-memorizing data bus system for random access data transfer

Claim 2

In a data bus system, the combination comprising: a. a bus conductor for transferring electrical signals: b. at least one input device connected to said bus for generating multi-state electrical signals indicative of data information; c. at least one output device connected to said bus conductor, said output device being operable, at random, to read said electrical signals from said bus conductor; and d. at least one non-inverting buffer having an input lead and an output lead, said input and said output leads being connected together to form a feedback loop and to said bus conductor to permit said buffer to be driven by said input device and to latch said buffer at the state of the last generated of said electrical signals when said buffer is not driven by said input device.

Claim 3

The combination as set forth in claim 1 wherein said buffer comprises: a. a CMOS device connected to said bus conductor; and b. a resistor connected in series with said CMOS device between said input and said output leads of said buffer.

Claim 4

In a data bus system, the combination comprising: a. a conductive bus; b. input means connected to said bus for intermittently writing data information onto said bus by driving said bus in a plurality of electrical states each indicative of data information; c. output means connected to said bus, said output means being selectively operable to read said data information off said bus at random; and d. buffer means connected to said bus for remembering the last driven state of said bus when said bus is not being driven by said input means.

Claim 5

In a data bus system, the combination comprising: a. a conductive bus; b. input means connected to said bus for intermittently writing data information onto said bus by driving said bus in a plurality of electrical states each indicative of data information; c. output means connected to said bus, said output means being selectively operable to read said data information off said bus at random; and d. buffer means connected to said bus for remembering the last driven state of said bus when said bus is not being driven by said input means.

Claim 6

In a data bus system in accordance with claim 3, the combination wherein said buffer means includes: a. a non-inverting device having an input lead and an output lead, said input lead and said output lead being connected to each other to form a feedback loop; and b. signal control means for controlling the relationship between said input lead and said output lead.

Claim 7

In a data bus system in accordance with Claim 4, wherein: a. said non-inverting device is a CMOS device; and b. said signal control means is a resistor connected in series with said CMOS device and connecting between said input lead and said output lead.

Claim 8

In a data bus system, the combination comprising: a. a bus conductor; b. a plurality of data inputs, each of said data inputs including: i. means for selectively and intermittently generating a plurality of electrical signals corresponding to data information; and ii. a plurality of drivers, each of said drivers being connected to said conductor for intermittently driving said conductor to an electrical state representing one of said electrical signals; c. a plurality of data outputs, each of said outputs being connected to said conductor for reading out at random the state of said conductor and producing an output signal indicative of the data information represented thereby; and d. a buffer connected to said conductor for maintaining said conductor at its last driven state, said buffer including: i. an input lead connected to said conductor; ii. a non-inverting CMOS device connected to said input lead; iii. a resistor connected in series with said CMOS device; and iv. an output lead connecting said resistor to said input lead to form a feedback loop for said buffer.

Claim 9

In a data bus system, the combination comprising: a. a bus conductor; b. a plurality of data inputs, each of said data inputs including: i. means for selectively and intermittently generating a plurality of electrical signals corresponding to data information; and ii. a plurality of drivers, each of said drivers being connected to said conductor for intermittently driving said conductor to an electrical state representing one of said electrical signals; c. a plurality of data outputs, each of said outputs being connected to said conductor for reading out at random the state of said conductor and producing an output signal indicative of the data information represented thereby; and d. a buffer connected to said conductor for maintaining said conductor at its last driven state, said buffer including: i. an input lead connected to said conductor; ii. a non-inverting CMOS device connected to said input lead; iii. a resistor connected in series with said CMOS device; and iv. an output lead connecting said resistor to said input lead to form a feedback loop for said buffer.