Semiconductor information storage devices

Claim 2

A semiconductor information storage device having a plurality of cells each to store an information bit, each cell comprising a bipolar transistor capable of conducting in both the forward and the reverse directions, the transistor having a significant current gain factor in both directions, and a capacitance connected to the collector of the transistor, there being associated with the cell, writing means to charge the capacitance with the transistor conducting in the reverse direction, and reading means to provide an output indicative of the charge state of the capacitance.

Claim 3

A semiconductor information storage device as claimed in claim 1 in which switching means is provided to connect selectively the writing means and the reading means to the cell.

Claim 4

A semiconductor information storage device as claimed in claim 2 having means to raise the base potential level of the transistor to a value at which the transistor is capable of conducting in either direction, and the switching means connects selectively the writing means and the reading means to the emitter of the transistor.

Claim 5

A semiconductor information storage device as claimed in claim 3 in which the transistor is arranged to conduct in the forward direction to discharge the capacitance, when the capacitance is charged, and the reading means is connected to the emitter of the transistor.

Claim 6

A semiconductor information storage device as claimed in claim 1 having means in association with the cell by which an information bit stored in the cell periodically is restored.

Claim 7

A semiconductor information storage device as claimed in claim 1 in which each cell is formed in a semiconductor body comprising an epitaxial layer of one conductivity type on a substrate of the same conductivity type, the bi-directionAl transistor of the cell having a collector of the opposite conductivity type comprising both a heavily doped isolation barrier for the transistor and a heavily doped buried layer at the interface between the epitaxial layer and the substrate, the isolation barrier extending through the epitaxial layer into contact with the buried layer, there being formed a P-N junction between the collector and parts of the semiconductor body around the collector and remote from the base, the capacitance of the cell being provided by said P-N junction.

Claim 8

A semiconductor information storage device as claimed in claim 1 in which the plurality of cells are formed in a single semiconductor body.

Claim 9

A semiconductor information storage device as claimed in claim 7 in which the writing means and the reading means are also formed in the semiconductor body.

Claim 10

A semiconductor information storage device having a plurality of cells each to store an information bit, each cell comprising a bipolar collector-diffusion-isolation transistor, the transistor having significant current gain factor in both directions, and a capacitance connected to the collector of the transistor, there being associated with the cell, writing means to charge the capacitance with the transistor conducting in the reverse direction, and reading means to provide an output indicative of the charged state of the capacitance.

Claim 11

A semiconductor information storage device having a plurality of cells each to store an information bit, each cell comprising a bipolar collector-diffusion-isolation transistor, the transistor having significant current gain factor in both directions, and a capacitance connected to the collector of the transistor, there being associated with the cell, writing means to charge the capacitance with the transistor conducting in the reverse direction, and reading means to provide an output indicative of the charged state of the capacitance.

Claim 12

A semiconductor information storage device as claimed in claim 9 in which switching means is provided to connect selectively the writing means and the reading means to the cell.

Claim 13

A semiconductor information storage device as claimed in claim 9 having means to raise the base potential level of the transistor to a value at which the transistor is capable of conducting in either direction, and the switching means connects selectively the writing means and the reading means to the emitter of the transistor.

Claim 14

A semiconductor information storage device as claimed in claim 11 in which the transistor is arranged to conduct in the forward direction to discharge the capacitance, when the capacitance is charged, and the reading means is connected to the emitter of the transistor.

Claim 15

A semiconductor information storage device as claimed in claim 9 having means in association with the cell by which an information bit stored in the cell periodically is restored.

Claim 16

A semiconductor information storage device as claimed in claim 9 in which each cell is formed in a semiconductor body comprising an epitaxial layer of one conductivity type on a substrate of the same conductivity type, the bi-directional transistor of the cell having a collector of the opposite conductivity type comprising both a heavily doped isolation barrier for the transistor and a heavily doped buried layer at the interface between the epitaxial layer and the substrate, the isolation barrier extending through the epitaxial layer into contact with the buried layer, there being formed a P-N junction between the collector and parts of the semiconductor body around the collector and remote from the base, the capacitance of the cell being provided by said P-N junction.

Claim 17

A semiconductor information storage device as claimed in claim 9 in which the plurality of cells are formed in a single semiconductor body.

Claim 18

A semiconductor information storage device as claimed in claim 15 in which the writing means and the reading means are also formed in the semiconductor body.