US5374569A
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Method for forming a BiCDMOS
Assignee: Vishay Siliconix Inc
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Filing: 1993-03-05
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Granted: 1994-12-20
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Expires: 2013-03-05
Abstract
Abstract A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
Inventors
- 👤 Hamza Yilmaz
- 👤 Richard K. Williams
- 👤 Michael E. Cornell
- 👤 Jun W. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:15
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D30/601; H10D30/603; H10D30/645; H10D30/66; H10D30/663; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/101; H10D84/40; H10D84/401; H10D84/403; H10D62/102; H10D62/112; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/085
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
277 words
A method for providing a plurality of electronic devices on a single wafer, said wafer comprising an epitaxial layer having an upper surface, said epitaxial layer being doped with a dopant of a first conductivity type, wherein an MOS transistor is formed in an MOS region of said wafer and a plurality of buried zener diodes are formed in a zener region of said wafer, said method comprising the steps of: (a) forming a plurality of laterally separated first zener portions into said upper surface of said epitaxial layer in said zener region, each of said first zener portions being doped with a dopant of a second conductivity type opposite said first conductivity type; (b) performing a light ion implantation step with a dopant of said first conductivity type to form simultaneously a source and a drain in said MOS region and to form simultaneously at least one second zener portion in said zener region, said light ion implantation step having a first dose; and (c) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a plurality of third zener portions into said zener region, to dope said source, and to form simultaneously a drain contact region within said drain, each of said plurality of third zener portions corresponding with and making contact one of said first zener portions to form one of said plurality of buried zener diodes, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, said ion implantation step having a second dose, wherein said second dose in higher than said first dose.
Claim 2
Independent Claim
277 words
A method for providing a plurality of electronic devices on a single wafer, said wafer comprising an epitaxial layer having an upper surface, said epitaxial layer being doped with a dopant of a first conductivity type, wherein an MOS transistor is formed in an MOS region of said wafer and a plurality of buried zener diodes are formed in a zener region of said wafer, said method comprising the steps of: (a) forming a plurality of laterally separated first zener portions into said upper surface of said epitaxial layer in said zener region, each of said first zener portions being doped with a dopant of a second conductivity type opposite said first conductivity type; (b) performing a light ion implantation step with a dopant of said first conductivity type to form simultaneously a source and a drain in said MOS region and to form simultaneously at least one second zener portion in said zener region, said light ion implantation step having a first dose; and (c) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a plurality of third zener portions into said zener region, to dope said source, and to form simultaneously a drain contact region within said drain, each of said plurality of third zener portions corresponding with and making contact one of said first zener portions to form one of said plurality of buried zener diodes, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, said ion implantation step having a second dose, wherein said second dose in higher than said first dose.
Claim 3
Dependent Claim
15 words
The method of claim 1, wherein said MOS transistor is an N channel MOS transistor.
Claim 4
Dependent Claim
77 words
The method of claim 1, wherein a first bipolar transistor is formed on said single wafer, said first bipolar transistor having a base region, said method further comprising the step of: ion implanting an emitter region of said first bipolar transistor into said base region of said first bipolar transistor during step (c) while said third zener portions are being implanted, while said source region is being implanted, and while said drain contact region is being implanted.
Claim 5
Dependent Claim
80 words
The method of claim 3, wherein a second bipolar transistor is formed on said single wafer, said second bipolar transistor having a base region, said method further comprising the step of: ion implanting a base contact region into said base region of said second bipolar transistor during step (c) while said third zener portions are being implanted, while said source region is being implanted, while said drain contact region is being implanted, and while said emitter region is being implanted.
Claim 6
Dependent Claim
34 words
The method of claim 4, wherein said MOS transistor is an N channel MOS transistor, said first bipolar transistor is a vertical NPN transistor, and said second bipolar transistor in a vertical PNP transistor.
Claim 7
Dependent Claim
82 words
The method of claim 1, wherein a DMOS transistor is formed on said single wafer, said DMOS transistor having a body region of said second conductivity type, said method further comprising the step of: ion implanting a DMOS source region into said body region of said DMOS transistor during step (c) while said third zener portions are being implanted, while said source region is being implanted, while said drain contact region is being implanted, and while said emitter region is being implanted.
Claim 8
Independent Claim
311 words
A method for providing a plurality of electronic devices on a single wafer, said wafer comprising an epitaxial layer having an upper surface, said epitaxial layer being doped with a dopant of a first conductivity type, wherein a DMOS transistor is formed in a DMOS region of said wafer and a plurality of buried zener diodes are formed in a zener region of said wafer, said method comprising the steps of: (a) forming a plurality of laterally separated first zener portions into said upper surface of said epitaxial layer in said zener region, each of said first zener portions being doped with a dopant of a second conductivity type opposite said first conductivity type; (b) performing a body ion implantation step with a dopant of said second conductivity type to form a body region in said upper surface of said epitaxial layer in said DMOS region, said body ion implantation step having a first dose; (c) performing a light ion implantation step with a dopant of said first conductivity type to form at least one second zener portion in said zener region, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, wherein said light ion implantation step introduces dopant of said first conductivity type into said body region, said light ion implantation step having a second dose, wherein said first dose is higher than said second dose; and (d) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a plurality of third zener portions into said zener region and to form simultaneously a DMOS source region within said body region, each of said plurality of third zener portions corresponding with and making contact with one of said first zener portions to form one of said plurality of buried zener diodes.
Claim 9
Independent Claim
311 words
A method for providing a plurality of electronic devices on a single wafer, said wafer comprising an epitaxial layer having an upper surface, said epitaxial layer being doped with a dopant of a first conductivity type, wherein a DMOS transistor is formed in a DMOS region of said wafer and a plurality of buried zener diodes are formed in a zener region of said wafer, said method comprising the steps of: (a) forming a plurality of laterally separated first zener portions into said upper surface of said epitaxial layer in said zener region, each of said first zener portions being doped with a dopant of a second conductivity type opposite said first conductivity type; (b) performing a body ion implantation step with a dopant of said second conductivity type to form a body region in said upper surface of said epitaxial layer in said DMOS region, said body ion implantation step having a first dose; (c) performing a light ion implantation step with a dopant of said first conductivity type to form at least one second zener portion in said zener region, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, wherein said light ion implantation step introduces dopant of said first conductivity type into said body region, said light ion implantation step having a second dose, wherein said first dose is higher than said second dose; and (d) performing an ion implantation step with a dopant of said first conductivity type to form simultaneously a plurality of third zener portions into said zener region and to form simultaneously a DMOS source region within said body region, each of said plurality of third zener portions corresponding with and making contact with one of said first zener portions to form one of said plurality of buried zener diodes.
Claim 10
Dependent Claim
25 words
The method of claim 7, wherein during body ion implantation step (b), dopant of said second conductivity type is introduced to said first zener portions.
Claim 11
Dependent Claim
183 words
A semiconductor structure comprising, an MOS transistor and a plurality of zener diodes on a single wafer, said single wafer comprising a semiconductor layer having an upper surface, said semiconductor layer having a first conductivity type, wherein said MOS transistor comprises a source, a drain and a drain contact region, each having said first conductivity type, and wherein said plurality of zener diodes comprises a plurality of laterally separated first zener portions formed into said upper surface of said semiconductor layer, each of said first zener portions having a second conductivity type opposite said first conductivity type; at least one second zener portion, said second zener portion having said first conductivity type, wherein said at least one second zener portion surrounds in a laterally oriented plane at least one of said plurality of first zener portions; and a plurality of third zener portions, said third zener portion having said first conductivity type, wherein each of said plurality of third zener portions corresponds with and makes contact with one of said first zener portions to form one of said plurality of buried zener diodes.
Claim 12
Dependent Claim
183 words
A semiconductor structure comprising, an MOS transistor and a plurality of zener diodes on a single wafer, said single wafer comprising a semiconductor layer having an upper surface, said semiconductor layer having a first conductivity type, wherein said MOS transistor comprises a source, a drain and a drain contact region, each having said first conductivity type, and wherein said plurality of zener diodes comprises a plurality of laterally separated first zener portions formed into said upper surface of said semiconductor layer, each of said first zener portions having a second conductivity type opposite said first conductivity type; at least one second zener portion, said second zener portion having said first conductivity type, wherein said at least one second zener portion surrounds in a laterally oriented plane at least one of said plurality of first zener portions; and a plurality of third zener portions, said third zener portion having said first conductivity type, wherein each of said plurality of third zener portions corresponds with and makes contact with one of said first zener portions to form one of said plurality of buried zener diodes.
Claim 13
Dependent Claim
16 words
The semiconductor structure of claim 9, wherein said MOS transistor is an N channel MOS transistor.
Claim 14
Dependent Claim
49 words
The semiconductor structure of claim 9, further comprising a first bipolar transistor formed on said single wafer, wherein said first bipolar transistor comprises a base region; and an emitter region implanted into said base region of said first bipolar transistor, wherein said emitter region has said first conductivity type.
Claim 15
Dependent Claim
51 words
The semiconductor structure of claim 11, further comprising a second bipolar transistor formed on said single wafer, wherein said second bipolar transistor comprises a base region; and a base contact region implanted in said base region of said second bipolar transistor, wherein said base contact region has said first conductivity type.
Claim 16
Dependent Claim
35 words
The semiconductor structure of claim 12, wherein said MOS transistor is an N channel MOS transistor, said first bipolar transistor is a vertical NPN transistor, and said second bipolar transistor is a vertical PNP transistor.
Claim 17
Dependent Claim
54 words
The semiconductor structure of claim 9, further comprising a DMOS transistor formed on said single wafer, wherein said DMOS transistor comprises a body region having said second conductivity type; and a DMOS source region having said first conductivity type, wherein said DMOS source region is implanted in said body region of said DMOS transistor.
Claim 18
Dependent Claim
200 words
A semiconductor structure comprising a DMOS transistor and a plurality of buried zener diodes formed on a single wafer, said single wafer having a semiconductor layer with an upper surface, said semiconductor layer being doped with a dopant of a first conductivity type, wherein said DMOS transistor comprises: a body region having a second conductivity type opposite said first conductivity type; and a DMOS source region within said body region, said DMOS source region having said first conductivity type; and wherein said plurality of buried zener diodes comprises: a plurality of laterally separated first zener portions formed into said upper surface of said semiconductor layer, each of said first zener portions having said second conductivity type; at least one second zener portion, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, said second zener portions having said first conductivity type; and a plurality of third zener portions, each of said plurality of third zener portions corresponding with and making contact with one of said first zener portions to form one of said plurality of buried zener diodes, said third zener portions having said first conductivity type.
Claim 19
Dependent Claim
200 words
A semiconductor structure comprising a DMOS transistor and a plurality of buried zener diodes formed on a single wafer, said single wafer having a semiconductor layer with an upper surface, said semiconductor layer being doped with a dopant of a first conductivity type, wherein said DMOS transistor comprises: a body region having a second conductivity type opposite said first conductivity type; and a DMOS source region within said body region, said DMOS source region having said first conductivity type; and wherein said plurality of buried zener diodes comprises: a plurality of laterally separated first zener portions formed into said upper surface of said semiconductor layer, each of said first zener portions having said second conductivity type; at least one second zener portion, said at least one second zener portion surrounding in a laterally oriented plane at least one of said plurality of first zener portions, said second zener portions having said first conductivity type; and a plurality of third zener portions, each of said plurality of third zener portions corresponding with and making contact with one of said first zener portions to form one of said plurality of buried zener diodes, said third zener portions having said first conductivity type.
References Cited (Backward Citations)
US4119440A
Cited
US4481706A
Cited
US4826780A
Cited
US4590664A
Cited
US4601760A
Cited
US4628341A
Cited
US4887142A
Cited
US4795716A
Cited
US4855244A
Cited
JPH0230187A
Cited
US5156989A
Cited
US5091760A
Cited
JPH03203377A
Cited
US5260228A
Cited
US5262345A
Cited
GB2253091A
Cited
US5179432A
Cited
US5243214A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |