Method of integrated circuit chips design

Claim 1

A computer implemented method of personalizing a gate array from a plurality of circuit cells that have been formed in a semiconductor substrate to a specified functional design in which a personalized gate array utilizes less than all of said plurality of circuit cells, comprising the steps of: generating a global metal data pattern and a circuit metal data pattern providing global interconnecting metallization and circuit metal interconnecting metallization for interconnecting less than all of said plurality of circuit cells to form said personalized gate array based upon said specified functional design; providing a fixed metal data pattern for providing fixed metal connecting metallization shapes to couple power to all of said plurality of circuit cells; identifying, in said fixed metal data pattern, fixed metal data related to fixed metal shapes that are unused in said personalized gate array; generating a modified fixed metal data pattern by deleting from said fixed metal data pattern fixed metal data related to said unused fixed metal shapes identified in said identification step; and generating a metallization data pattern for said gate array by combining said circuit metal data pattern, said global metal data pattern and said modified fixed metal data pattern.