US4960724A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for deleting unused gates and method for manufacturing master-slice semiconductor integrated circuit device using the deleting method
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1989-07-11
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Granted: 1990-10-02
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Expires: 2009-07-11
Abstract
Abstract A method is provided for manufacturing a master slice semiconductor integrated circuit device. Initially, a first total circuit diagram which is to be reformed into a master slice semiconductor integrated circuit device is defined. First and second circuit points on the first total circuit block which are to be used respectively as input and output terminals of the master slice semiconductor integrated circuit device are specified. Next, signal transmitting paths are successively traced from the output to the input of each logic gate located in the signal transmitting paths in actual use. In the course of the tracing, these traced gates are marked and the logic gates actually in use are identified. As a result, in addition to those logic gates having unused output terminals, the gates constituting a closed loop isolated from the signal transmitting paths for transmitting substantial output signals are identified as unnecessary gates and deleted. Further, gates outputting only a fixed value are determined and designated unnecessary gates which are also deleted.
Inventors
- 👤 Shoichi Watanabe
- 👤 Takayuki Takei
- 👤 Terumine Hayashi
- 👤 Takashi Natabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:30
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/39
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
146 words
A method for deleting unused gates for use in converting first total circuit diagrams formed of a plurality of integrated circuit devices into second total circuit diagrams adapted for forming a single-chip semiconductor integrated circuit device, the method comprising the steps of: (1) specifying first circuit points to be used as external terminals for outputting signals and second circuit points to be used as external terminals for inputting signals of said semiconductor integrated circuit device on said first total circuit diagrams; (2) tracing signal transmitting paths between said first circuit points and said second circuit points starting from said first circuit points and advancing toward said second circuit points to thereby detect logic gates included in said signal transmitting paths; and (3) forming said second total circuit diagrams by deleting logic gates other than those detected in said step (2) from said first total circuit diagrams.
Claim 2
Independent Claim
146 words
A method for deleting unused gates for use in converting first total circuit diagrams formed of a plurality of integrated circuit devices into second total circuit diagrams adapted for forming a single-chip semiconductor integrated circuit device, the method comprising the steps of: (1) specifying first circuit points to be used as external terminals for outputting signals and second circuit points to be used as external terminals for inputting signals of said semiconductor integrated circuit device on said first total circuit diagrams; (2) tracing signal transmitting paths between said first circuit points and said second circuit points starting from said first circuit points and advancing toward said second circuit points to thereby detect logic gates included in said signal transmitting paths; and (3) forming said second total circuit diagrams by deleting logic gates other than those detected in said step (2) from said first total circuit diagrams.
Claim 3
Dependent Claim
78 words
The method for deleting unused gates according to claim 1, wherein said step (2) includes the steps of: (i) tracing each logic gate existing in said signal transmitting paths only in an opposite direction from its output to its input, and (ii) identifying logic gates which are traced in said step (i), and wherein said steps (i) and (ii) are repeated until said signal transmitting paths are traced from said first circuit points to said second circuits points.
Claim 4
Dependent Claim
43 words
The method for deleting unused gates according to claim 1, wherein each of said plurality of integrated circuit devices constituting said first total circuit diagrams is contained in a single package and has a plurality of external terminals for inputting and outputting signals.
Claim 5
Independent Claim
132 words
A method for converting first total circuit diagrams formed of a plurality of functional blocks into second total circuit diagrams adapted for forming a single-chip semiconductor integrated circuit device comprising the steps of: (1) detecting first circuit points and second circuit points on said first total circuit diagrams, which respectively correspond to output terminals and input terminals of said semiconductor integrated circuit device; (2) tracing signal transmitting paths between said first circuit points and said second circuit points starting from said first circuit points thereby detecting logic gates included in said signal transmitting paths, wherein said tracing proceeds in a direction opposite to a signal transmitting direction; and (3) causing said first total circuit diagrams to be reformed into said second total circuit diagrams responding to information detected in said step (2).
Claim 6
Independent Claim
132 words
A method for converting first total circuit diagrams formed of a plurality of functional blocks into second total circuit diagrams adapted for forming a single-chip semiconductor integrated circuit device comprising the steps of: (1) detecting first circuit points and second circuit points on said first total circuit diagrams, which respectively correspond to output terminals and input terminals of said semiconductor integrated circuit device; (2) tracing signal transmitting paths between said first circuit points and said second circuit points starting from said first circuit points thereby detecting logic gates included in said signal transmitting paths, wherein said tracing proceeds in a direction opposite to a signal transmitting direction; and (3) causing said first total circuit diagrams to be reformed into said second total circuit diagrams responding to information detected in said step (2).
Claim 7
Independent Claim
186 words
A method for manufacturing a master slice semiconductor integrated circuit device comprising the steps of: (a) defining first total circuit block diagrams to be reformed into said master slice semiconductor integrated circuit device; (b) specifying first circuit points to be used as output terminals and second circuit points to be used as input terminals of said master slice semiconductor integrated circuit device on said first total circuit block diagrams determined in said step (a); (c) representing said first total circuit block diagrams by a plurality of basic logic gates; (d) detecting basic logic gates included in signal transmitting paths between said first circuit points and said second circuit points; (e) reforming said first total circuit block diagrams into second total circuit diagrams for said master slice semiconductor integrated circuit device by deleting basic logic gates other than the basic logic gates detected in said step (d) from the basic logic gates constituting said first total circuit block diagrams; and, (f) producing a plurality of photomasks for forming said master slice semiconductor integrated circuit device based on the second total circuit diagrams formed in said step (e).
Claim 8
Independent Claim
186 words
A method for manufacturing a master slice semiconductor integrated circuit device comprising the steps of: (a) defining first total circuit block diagrams to be reformed into said master slice semiconductor integrated circuit device; (b) specifying first circuit points to be used as output terminals and second circuit points to be used as input terminals of said master slice semiconductor integrated circuit device on said first total circuit block diagrams determined in said step (a); (c) representing said first total circuit block diagrams by a plurality of basic logic gates; (d) detecting basic logic gates included in signal transmitting paths between said first circuit points and said second circuit points; (e) reforming said first total circuit block diagrams into second total circuit diagrams for said master slice semiconductor integrated circuit device by deleting basic logic gates other than the basic logic gates detected in said step (d) from the basic logic gates constituting said first total circuit block diagrams; and, (f) producing a plurality of photomasks for forming said master slice semiconductor integrated circuit device based on the second total circuit diagrams formed in said step (e).
References Cited (Backward Citations)
US4602339A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-01 | 1994-04-02 | 1994-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-01 | 1998-04-02 | 1998-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-01 | 2002-04-02 | 2002-10-02 | $7700.00 | Window Closed / Lapsed |