Semiconductor memory having memory cell units each including cascade-connected MOS transistors

Claim 2

A semiconductor memory comprising: a memory cell array formed of a plurality of memory cell units, each of the memory cell units including: a first node for reading data; a first cascade gate including a plurality of cascade-connected first MOS transistors and having a one end connected to said first node; and a plurality of capacitors for data storage each having a first electrode connected to one of said first MOS transistors at an end of said one first MOS transistor remote from said first node, said capacitors having a predetermined relationship with respect to each capacitance of said capacitors; and word lines respectively connected to gates of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors, wherein data stored in said capacitors is output to said first node in a sequence, and the predetermined relationship of said capacitors is such that the capacitor whose data is output last in said sequence has a greater capacitance than the capacitor whose data is output first in said sequence.

Claim 3

A semiconductor memory comprising: a memory cell array formed of a plurality of memory cell units, each of the memory cell units including: a first node for reading data; a second node for writing data; a first cascade gate including at least three cascade-connected first MOS transistors arranged between said first node and said second node; and a plurality of capacitors for data storage each having a first electrode connected to a connection node between adjacent ones of said first MOS transistors, said capacitors having a predetermined relationship with respect to each capacitance of said capacitors; and word lines respectively connected to gates of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors; wherein data stored in said capacitors is output to said first node in a sequence, and the predetermined relationship of said capacitors is such that the capacitor whose data is output last in said sequence has a greater capacitance than the capacitor whose data is output first in said sequence.

Claim 4

A semiconductor memory comprising: a memory cell array formed of a plurality of memory cell units, each of the memory cell units including: a first node for reading data; a second node for writing data; a first cascade gate including at least three cascade-connected first MOS transistors arranged between said first node and said second node; and a plurality of capacitors for data storage each having a first electrode connected to a connection node between adjacent ones of said first MOS transistors, said capacitors having a predetermined relationship with respect to each capacitance of said capacitors; and word lines respectively connected to gates of said first MOS transistors for supplying signals to control the ON/OFF switching of said first MOS transistors; wherein data stored in said capacitors is output to said first node in a sequence, and the predetermined relationship of said capacitors is such that the capacitor whose data is output last in said sequence has a greater capacitance than the capacitor whose data is output first in said sequence.

Claim 5

The semiconductor memory according to claim 2, wherein said first node and said second node are connected to each other.

Claim 6

The semiconductor memory according to claim 1 or 2, wherein the relationship relates to the order of outputting data from said capacitors.

Claim 7

The semiconductor memory according to claim 4, wherein relationship is set such that the more remote from said first node the capacitors of the memory cell are located, the larger capacitance they have.

Claim 8

The semiconductor memory according to claim 1 or 2, wherein said first node is connected to a bit line of a memory cell array.

Claim 9

The semiconductor memory according to claim 1 or 2, wherein second electrodes of said capacitors are commonly connected to a wiring.

Claim 10

The semiconductor memory according to claim 1 or 2, wherein said capacitors have a common plate electrode, and a predetermined capacitor plate potential is applied to said common plate electrode.

Claim 11

The semiconductor memory according to claim 1 or 2, wherein second electrodes of said capacitors are respectively connected to one of a plurality of different wirings.

Claim 12

The semiconductor memory according to claim 1 or 2, wherein the memory cell further comprises a second cascade gate including a plurality of cascade-connected second MOS transistors, the number of said second MOS transistors being equal to the number of first MOS transistors, each of said second MOS transistors having one end connected to a second electrode of one of said capacitors and each of said second MOS transistors having a gate connected to a gate of one of said first MOS transistors.

Claim 13

The semiconductor memory according to claim 10, wherein said first node and one end of said second cascade gate are respectively connected to first and second complementary bit lines of a memory cell array.

Claim 14

The semiconductor memory according to claim 2, further comprising: a second cascade gate including a plurality of cascade-connected second MOS transistors, the number of said second MOS transistors being equal to the number of first MOS transistors, each of said second MOS transistors having one end connected to a second electrode of one of said capacitors and each of said second MOS transistors having a gate connected to a gate of one of said first MOS transistors, wherein said first node and one end of said second cascade gate are respectively connected to first and second complementary bit lines of a memory cell array and said second node and another end of said second cascade gate are respectively connected to third and fourth complementary bit lines.

Claim 15

The semiconductor memory according to claim 2, further comprising: a second cascade gate including a plurality of cascade-connected second MOS transistors, the number of said second MOS transistors being equal to the number of first MOS transistors, each of said second MOS transistors having one end connected to a second electrode of one of said capacitors and each of said second MOS transistors having a gate connected to a gate of one of said first MOS transistors, wherein said first node and said second node are connected to each other, and one end and another end of said second cascade gate are connected to each other.

Claim 16

The semiconductor memory according to claim 13, wherein the connection point between said first node and said second node is connected to a first bit line of a memory cell array, and the connection point between said one end and said another end of said second cascade gate is connected to a second bit line complementary to said first bit line.

Claim 17

The semiconductor memory according to claim 1, wherein said memory cell unit is of stacked cell structure constructed such that the source, drain and channel regions of each of said first MOSD transistors are linearly arranged on a semiconductor substrate surface, and storage electrodes of said capacitors are in contact with the source regions or drain regions of the first MOS transistors.

Claim 18

The semiconductor memory according to claim 15, wherein said memory cell unit comprises four first MOS transistors and four capacitors.

Claim 19

The semiconductor memory according to clam 2, wherein said memory cell unit is of stacked cell structure constructed such that the source, drain and channel regions of each of said cascade-connected first MOS transistors are linearly arranged on a semiconductor substrate surface, and storage electrodes of said capacitors are in contact with the source-drain regions of the cascade-connected first MOS transistors

Claim 20

The semiconductor memory according to clam 2, wherein said memory cell unit is of stacked cell structure constructed such that the source, drain and channel regions of each of said cascade-connected first MOS transistors are linearly arranged on a semiconductor substrate surface, and storage electrodes of said capacitors are in contact with the source-drain regions of the cascade-connected first MOS transistors

Claim 21

The semiconductor memory according to claim 17, wherein said memory cell unit comprises five first MOS transistors and four capacitors.

Claim 22

The semiconductor memory according to claim 1 or 2, wherein said memory cell unit is of cross-point cell structure constructed such that said first MOS transistors and said capacitors are at least partially stacked one upon the other in the vertical direction

Claim 23

The semiconductor memory according to claim 1 or 2, further comprising: a precharge circuit for precharging said first node to a predetermined potential prior to outputting data from said capacitors.

Claim 24

The semiconductor memory according to claim 1 or 2, wherein the predetermined relationship of said capacitors is given by C.sub.n =C.sub.1 *{b+(C.sub.1 /C.sub.B)}.sup.n-1 where C 1 is the capacitance of the capacitor whose data is output first in said sequence, C n is the capacitance of the capacitor whose data is output nth is said sequence, and C B is the floating capacitance connected to said first node.

Claim 25

A semiconductor memory, comprising; a first read/write data node; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said first terminal of said second MOS transistor connected to said second terminal of said first MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and second MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein the second capacitance is greater than the first capacitance.

Claim 26

A semiconductor memory, comprising; a first read/write data node; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said first terminal of said second MOS transistor connected to said second terminal of said first MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and second MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein the second capacitance is greater than the first capacitance.

Claim 27

The semiconductor memory according to claim 2, further comprising: word lines respectively connected to gates of said first and second MOS transistors for supplying signals to control the ON/OFF switching of said first and second MOS transistors.

Claim 28

The semiconductor memory according to claim 23, wherein said signals switch said first and second MOS transistors such that data is sequentially read and sequentially written to said data storage capacitors, the signals switching said first MOS transistor ON, subsequently switching said second MOS transistor ON, subsequently switching said second MOS transistor OFF, and subsequently switching said first MOS transistor OFF.

Claim 29

The semiconductor memory according to claim 24, further comprising: a precharge circuit for precharging said first read/write data node to a predetermined potential prior to outputting data from said first and second data storage capacitors.

Claim 30

The semiconductor memory according to claim 24, further comprising: a sense amplifier for sensing data output to said first read/write data node.

Claim 31

The semiconductor memory according to claim 23, further comprising: a write circuit for supplying data t said first read/write data node for writing to said first and second data storage capacitors.

Claim 32

The semiconductor memory according to claim 27, wherein said signals switch said first and second MOS transistors such that data supplied to said first read/write data node by said write circuit is sequentially written to said first and second data storage capacitors.

Claim 33

The semiconductor memory according to claim 22, wherein said first and second data storage capacitors each comprise first and second electrodes, said first electrodes respectively connected to said second terminal of each of said first and second MOS transistors and said second electrodes connected to a predetermined potential.

Claim 34

The semiconductor memory according to claim 22, wherein: each of said first and second MOS transistors has a drain region corresponding to said first terminal thereof, a source region corresponding to said second terminal thereof, and a channel region located between said drain and source regions, said drain, channel, and source regions of each of said first and second MOS transistors arranged linearly on a surface of a semiconductor substrate; and each of said first and second data storage capacitors has a storage electrode an insulating film, and a plate electrode, said first data storage capacitor having a stack structure wherein said storage electrode of said first data storage capacitor contacts said source region of said first MOS transistor and said second data storage capacitor having a stack structure wherein said storage electrode of said second data storage capacitor contacts said source region of said second MOS transistor.

Claim 35

A semiconductor memory, comprising: a first read/write data node; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said first terminal of said second MOS transistor connected to said second terminal of said first MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and second MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein: each of said first and second MOS transistor has a drain region corresponding t said first terminal thereof, a source region corresponding to said second terminal thereof, and a channel region located between said drain and source regions, said drain region of said first MOS transistor formed on an upper surface of a projection formed on a surface of a semiconductor substrate, said channel and source regions of said first MOS transistor formed on a side surface of said projection, and said drain, channel and source regions of said second MOS transistor formed on said side surface of said projection and located below said source region of said first MOS transistor; and each of said first and second data storage capacitors has a storage electrode, an insulating film, and a plate electrode, said storage electrode of said first data storage capacitor located on said side surface of said projection and extending continuously between said source region of said first MOS transistor and said drain region of said second MOS transistor and said storage electrode of said second data storage capacitor located on said side surface of said projection and extending continuously in said source region of said second MOS transistor.

Claim 36

A semiconductor memory, comprising: a first read/write data node; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said first terminal of said second MOS transistor connected to said second terminal of said first MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and second MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein: each of said first and second MOS transistor has a drain region corresponding t said first terminal thereof, a source region corresponding to said second terminal thereof, and a channel region located between said drain and source regions, said drain region of said first MOS transistor formed on an upper surface of a projection formed on a surface of a semiconductor substrate, said channel and source regions of said first MOS transistor formed on a side surface of said projection, and said drain, channel and source regions of said second MOS transistor formed on said side surface of said projection and located below said source region of said first MOS transistor; and each of said first and second data storage capacitors has a storage electrode, an insulating film, and a plate electrode, said storage electrode of said first data storage capacitor located on said side surface of said projection and extending continuously between said source region of said first MOS transistor and said drain region of said second MOS transistor and said storage electrode of said second data storage capacitor located on said side surface of said projection and extending continuously in said source region of said second MOS transistor.

Claim 37

The semiconductor memory according to claim 22, wherein aid first and second data storage capacitors each comprise first and second electrodes, said first electrodes respectively connected to said second terminal of said first and second MOS transistors and said second electrodes receiving respective clock signals.

Claim 38

The semiconductor memory according to claim 22, further comprising: a second read/write data node; a third MOS transistor having first and second terminals, said first terminal of said third MOS transistor connected to said second read/write data node; a fourth MOS transistor having first and second terminals, said first terminal of said fourth MOS transistor connected to said second terminal of said third MOS transistor, wherein said first data storage capacitor is connected between said second terminal of said first MOS transistor and said second terminal of said third MOS transistor, and said second data storage capacitor is connected between said second terminal of said second MOS transistor and said second terminal of said fourth MOS transistor.

Claim 39

A semiconductor memory, comprising: first and second rad/write data nodes; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said second terminal of said second MOS transistor connected to said second read/write data node; a third MOS transistor having first and second terminals respectively coupled between said second terminal of said first MOS transistor and said first terminal of said second MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and third MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein the second capacitance is greater than the first capacitance.

Claim 40

A semiconductor memory, comprising: first and second rad/write data nodes; a first MOS transistor having first and second terminals, said first terminal of said first MOS transistor connected to said first read/write data node; a second MOS transistor having first and second terminals, said second terminal of said second MOS transistor connected to said second read/write data node; a third MOS transistor having first and second terminals respectively coupled between said second terminal of said first MOS transistor and said first terminal of said second MOS transistor; first and second data storage capacitors respectively connected to said second terminals of said first and third MOS transistors, said first data storage capacitor having a first capacitance and said second data storage capacitor having a second capacitance for compensating a voltage variation at said first read/write data node when data is sequentially output from said first and second data storage capacitors, wherein the second capacitance is greater than the first capacitance.

Claim 41

The semiconductor memory according to claim 34, wherein said first and second read/write data nodes are connected to each other.

Claim 42

The semiconductor memory according to claim 34, further comprising: word lines respectively connected to gates of said first, second, and third MOS transistors for supplying signals to control the ON/OFF switching of said first, second, and third MOS transistors.

Claim 43

The semiconductor memory according to claim 36, wherein said signals switch said first, second, and third MOS transistors such that data is sequentially read and sequentially written to said data storage capacitors, the signals switching said first MOS transistor ON, subsequently switching said third OS transistor ON, subsequently switching said second MOS transistor ON, subsequently switching said first MOS transistor OFF, subsequently switching said third MOS transistor OFF, and subsequently switching said second MOS transistor OFF.

Claim 44

The semiconductor memory according to claim 37, further comprising: a precharge circuit for precharging said first and second read/write data nodes to a predetermined potential prior outputting data from said first and second data storage capacitors.

Claim 45

The semiconductor memory according to claim 37, further comprising: a sense amplifier for sensing data output to said first and second read/write data nodes.

Claim 46

The semiconductor memory according to claim 36, further comprising: a write circuit for supplying data to said first and second read/write data nodes for writing to said first and second data storage capacitors.

Claim 47

The semiconductor memory according to claim 40, wherein said signals switch said first, second, and third MOS transistors such that data at said first and second read/write data nodes is sequentially written to said first and second data storage capacitors.

Claim 48

The semiconductor memory according to claim 34, wherein said first and second data storage capacitors each comprise first and second electrodes, said first electrodes respectively connected to said second terminal of said first and third MOS transistors and said second electrodes each connected to a predetermined potential.

Claim 49

The semiconductor memory according to claim 34, further comprising: third and fourth read/write data nodes; a fourth MOS transistor having first and second terminals, said first terminal of said fourth MOS transistor connected to said third read/write data node; a fifth MOS transistor having first and second terminals, said second terminal of said fifth MOS transistor connected to said fourth read/write data node; a sixth MOS transistor having first and second terminals respectively coupled between said second terminal of said fourth MOS transistor and said first terminal of said fifth transistor, wherein said first data storage capacitor is connected between said second terminal of said first MOS transistor and said second terminal of said fourth MOS transistor, and said second data storage capacitor is connected between said second terminal of said third MOS transistor and said second terminal of said sixth MOS transistor.