US5339275A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog memory system
Assignee: Individual
•
Filing: 1990-03-16
•
Granted: 1994-08-16
•
Expires: 2010-03-16
Abstract
Abstract An improved analog memory arrangement is interfaced to receive digital signals through a digital to analog converter and is interfaced to output analog signals through an analog to digital converter. Analog refreshing is implemented to reduce degradation of analog signals stored by the analog memory including scale factor refreshing and bias refreshing. The analog memory is particularly suitable for illumination signal processing and for storing display images to be displayed.
Inventors
- 👤 Gilbert P. Hyatt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:34
CPC Classifications
B; B60; B60R; B60R16/00; B60R16/02; B60R16/037; B60R16/0373; F; F21; F21V; F21V23/00; G; G01; G01S; G01S15/00; G01S15/88; G01S15/89; G01S15/8906; G01S15/8965; G01S15/897; G01S15/8977; G01S7/00; G01S7/52; G01S7/52017; G01S7/52023; G01S7/52025; G01S7/52026; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/13306; G02F1/13318; G03; G03F; G03F9/00; G03F9/70; G03F9/7049; G03F9/7088; G04; G04G; G04G99/00; G04G99/006; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/33; G05B19/35; G05B19/351; G05B19/408; G05B19/4083; G05B19/4086; G05B19/409; G05B19/4093; G05B19/414; G05B19/4142; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06J; G06J1/00; G07; G07G; G07G1/00; G07G1/12; G10; G10L; G10L19/00; G11; G11C; G11C11/00; G11C11/56; G11C11/565; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3431; G11C19/00; G11C19/28; G11C19/287; G11C19/34; G11C19/36; G11C27/00; G11C27/02; G11C27/024; G11C27/04; G11C7/00; G11C7/10; G11C7/1015; G11C7/1042; G05B2219/00; G05B2219/30; G05B2219/33; G05B2219/33182; G05B2219/34; G05B2219/34023; G05B2219/34098; G05B2219/34471; G05B2219/34472; G05B2219/35; G05B2219/35262; G05B2219/35263; G05B2219/35373; G05B2219/35431; G05B2219/35436; G05B2219/35453; G05B2219/35472; G05B2219/35554; G05B2219/36; G05B2219/36152; G05B2219/36333; G05B2219/36366; G05B2219/36379; G05B2219/36503; G05B2219/36546; G05B2219/41; G05B2219/41021; G05B2219/42; G05B2219/42237; G05B2219/45; G05B2219/45214; G05B2219/45215; G05B2219/49; G05B2219/49221; G05B2219/50; G05B2219/50047; G05B2219/50048; G05B2219/50083; G05B2219/50151; G11C7/16
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
141 words
An analog memory system comprising: a shiftable analog memory storing analog signals; a shifting circuit coupled to the shiftable analog memory and shifting the analog signals stored by the shiftable analog memory; an analog to digital converter coupled to the shiftable analog memory and generating digital output signals in response to the analog signals stored by the shiftable analog memory; and a digital filter processor coupled to the analog to digital converter and generating filtered digital signal samples by filter processing the digital output signals, wherein the filter processor includes a) a digital weighting circuit coupled to the analog to digital converter and generating weighted digital signal samples in response to the digital output signals and b) a digital summing circuit coupled to the digital weighting circuit and generating filtered digital signal samples in response to the weighted digital signal samples.
Claim 2
Dependent Claim
141 words
An analog memory system comprising: a shiftable analog memory storing analog signals; a shifting circuit coupled to the shiftable analog memory and shifting the analog signals stored by the shiftable analog memory; an analog to digital converter coupled to the shiftable analog memory and generating digital output signals in response to the analog signals stored by the shiftable analog memory; and a digital filter processor coupled to the analog to digital converter and generating filtered digital signal samples by filter processing the digital output signals, wherein the filter processor includes a) a digital weighting circuit coupled to the analog to digital converter and generating weighted digital signal samples in response to the digital output signals and b) a digital summing circuit coupled to the digital weighting circuit and generating filtered digital signal samples in response to the weighted digital signal samples.
Claim 3
Dependent Claim
25 words
An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog charge transfer device storing the analog signals.
Claim 4
Dependent Claim
25 words
An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog magnetic disk memory storing the analog signals.
Claim 5
Dependent Claim
25 words
An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog magnetic bubble memory storing the analog signals.
Claim 6
Dependent Claim
112 words
An analog memory system comprising: an analog memory storing analog signals; a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signals stored by the analog memory; a converter coupled to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory; and a filter processor including a multiplier coupled to the converter and generating digital product signals in response to the digital output signals and an adder coupled to the multiplier and generating digital filtered signals by adding the digital product signals.
Claim 7
Dependent Claim
112 words
An analog memory system comprising: an analog memory storing analog signals; a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signals stored by the analog memory; a converter coupled to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory; and a filter processor including a multiplier coupled to the converter and generating digital product signals in response to the digital output signals and an adder coupled to the multiplier and generating digital filtered signals by adding the digital product signals.
Claim 8
Dependent Claim
129 words
An analog memory system comprising: a charge memory storing multiple state charge signals having an information content related to the signal state; a refresh circuit coupled to the charge memory and refreshing the stored multiple state charge signals to reduce amplitude degradation; a shifting circuit coupled to the charge memory and shifting the multiple state charge signals stored by the charge memory; a converter coupled to the charge memory and generating digital output signals in response to the multiple state charge signals stored by the charge memory; and a filter processor including a weighting circuit coupled to the converter and generating weighted digital signals in response to the digital output signals and an integrator coupled to the multiplier and generating digital filtered signals by integrating the digital product signals.
Claim 9
Dependent Claim
129 words
An analog memory system comprising: a charge memory storing multiple state charge signals having an information content related to the signal state; a refresh circuit coupled to the charge memory and refreshing the stored multiple state charge signals to reduce amplitude degradation; a shifting circuit coupled to the charge memory and shifting the multiple state charge signals stored by the charge memory; a converter coupled to the charge memory and generating digital output signals in response to the multiple state charge signals stored by the charge memory; and a filter processor including a weighting circuit coupled to the converter and generating weighted digital signals in response to the digital output signals and an integrator coupled to the multiplier and generating digital filtered signals by integrating the digital product signals.
Claim 10
Dependent Claim
147 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and a filter processor including a weighting circuit coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.
Claim 11
Dependent Claim
147 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and a filter processor including a weighting circuit coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.
Claim 12
Dependent Claim
143 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; a reference circuit generating an analog reference signal; and a refresh circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the analog reference signal.
Claim 13
Dependent Claim
143 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; a reference circuit generating an analog reference signal; and a refresh circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the analog reference signal.
Claim 14
Dependent Claim
92 words
An analog memory system comprising: an analog read only memory storing an analog memory signal; a shifting circuit coupled to the analog memory and shifting the analog memory signal stored by the analog read only memory; and a filter processor including a weighting circuit coupled to the analog read only memory and generating a weighted analog signal in response to the analog memory signal stored by the analog read only memory and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.
Claim 15
Dependent Claim
92 words
An analog memory system comprising: an analog read only memory storing an analog memory signal; a shifting circuit coupled to the analog memory and shifting the analog memory signal stored by the analog read only memory; and a filter processor including a weighting circuit coupled to the analog read only memory and generating a weighted analog signal in response to the analog memory signal stored by the analog read only memory and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.
Claim 16
Dependent Claim
85 words
An analog memory system as set forth in claim 7, wherein the analog input signal stored by the analog memory is a multiple state signal having an information content related to the signal state and wherein the analog memory includes a charge circuit storing the multiple state analog input signal as a multiple state charge signal; wherein the system further comprises a refresh circuit coupled to the analog memory and refreshing the multiple state signal stored by the analog memory to reduce charge leakage degradation.
Claim 17
Dependent Claim
167 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory; and a filter processor coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.
Claim 18
Dependent Claim
167 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory; and a filter processor coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.
Claim 19
Dependent Claim
107 words
An analog memory system comprising: an analog memory storing analog signals, wherein the storing of the analog signals causes degradation of the analog signals; a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory; a refresh circuit coupled to the analog memory and refreshing the analog signals to reduce degradation thereof; and a filter processor including a weighting circuit coupled to the analog memory and generating a weighted analog signal in response to the analog signals stored therein and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.
Claim 20
Dependent Claim
107 words
An analog memory system comprising: an analog memory storing analog signals, wherein the storing of the analog signals causes degradation of the analog signals; a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory; a refresh circuit coupled to the analog memory and refreshing the analog signals to reduce degradation thereof; and a filter processor including a weighting circuit coupled to the analog memory and generating a weighted analog signal in response to the analog signals stored therein and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.
Claim 21
Dependent Claim
97 words
An analog memory system as set forth in claim 12, further comprising: a digital input circuit generating digital input signals; a digital to analog converter coupled to the digital input circuit and generating analog input signals in response to the digital input signal; a writing circuit coupled to the analog memory and to the digital to analog to digital converter and writing the analog input signals into the analog memory; and an analog to digital converter coupled to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory.
Claim 22
Dependent Claim
69 words
An analog memory system as set forth in claim 12, further comprising: a digital input circuit generating digital input signals; a digital to analog converter coupled to the digital input circuit and generating analog input signals in response to the digital input signals; and a writing circuit coupled to the digital to analog converter and to the analog memory and writing the analog input signals into the analog memory.
Claim 23
Dependent Claim
37 words
An analog memory system as set forth in claim 12, further comprising a digital output circuit connected to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory.
Claim 24
Dependent Claim
76 words
An analog memory system as set forth in claim 1, wherein the analog signals stored by the shiftable analog memory includes an analog stored program, wherein the digital output signals generated by the analog to digital converter include stored program digital output signals, and wherein the filter processor includes a stored program digital computer coupled to the analog to digital converter and processing the digital output signals by execution of the stored program digital output signals.
Claim 25
Dependent Claim
61 words
An analog memory system as set forth in claim 1, further comprising: an analog input circuit coupled to the filter processor and generating analog input signals in response to the filtered digital signal samples; and a writing circuit coupled to the analog input circuit and to the shiftable analog memory and writing the analog input signals into the shiftable analog memory.
Claim 26
Dependent Claim
43 words
An analog memory system as set forth in claim 1, further comprising: a writing circuit coupled to the filter processor and to the shiftable analog memory and writing analog signals into the shiftable analog memory in response to the filtered digital signal samples.
Claim 27
Dependent Claim
57 words
An analog memory system as set forth in claim 7, further comprising: a digital to analog converter coupled to the analog to digital converter and generating an analog output signal and an analog writing circuit coupled to the digital to analog converter and to the analog memory and writing the analog output signal into the analog memory.
Claim 28
Dependent Claim
136 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal, wherein the analog input signal stored by the analog memory includes a stored program; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and a stored program digital computer processing the digital output signal in response to the stored program stored by the analog memory.
Claim 29
Dependent Claim
136 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal, wherein the analog input signal stored by the analog memory includes a stored program; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and a stored program digital computer processing the digital output signal in response to the stored program stored by the analog memory.
Claim 30
Dependent Claim
24 words
An analog memory system as set forth in claim 7, wherein the analog memory includes an analog read only memory storing the analog signals.
Claim 31
Dependent Claim
30 words
An analog memory system as set forth in claim 7, wherein the analog memory is a charge transfer device memory storing the analog input signal as an analog charge signal.
Claim 32
Dependent Claim
31 words
An analog memory system as set forth in claim 7, wherein the analog memory is an analog magnetic bubble memory storing the analog input signal as an analog magnetic bubble signal.
Claim 33
Dependent Claim
30 words
An analog memory system as set forth in claim 7, wherein the analog memory is an analog magnetostrictive delay line memory storing the analog signal as an analog magnetostrictive signal.
Claim 34
Dependent Claim
49 words
An analog memory system as set forth in claim 11, wherein amplitude of the analog signal stored by the analog memory is degraded by the storing thereby and wherein the system further comprises a refresh circuit coupled to the analog memory and reducing degradation of the stored analog signal.
Claim 35
Dependent Claim
197 words
An analog memory system comprising: a digital input circuit generating a digital input signal;. a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory, wherein the refresh circuit includes: a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory, a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number for amplitude degradation, and a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number; and an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory.
Claim 36
Dependent Claim
197 words
An analog memory system comprising: a digital input circuit generating a digital input signal;. a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory, wherein the refresh circuit includes: a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory, a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number for amplitude degradation, and a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number; and an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory.
Claim 37
Dependent Claim
175 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory; a digital processor coupled to the analog to digital converter and processing the digital output signal; and a writing circuit coupled to the digital processor and to the analog memory and writing an analog signal into the analog memory in response to the digital output signal processed by the digital processor.
Claim 38
Dependent Claim
175 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory; a digital processor coupled to the analog to digital converter and processing the digital output signal; and a writing circuit coupled to the digital processor and to the analog memory and writing an analog signal into the analog memory in response to the digital output signal processed by the digital processor.
Claim 39
Dependent Claim
53 words
An analog memory system as set forth in claim 11, wherein the analog signal stored by the analog memory includes a stored program, and wherein the filter processor includes a stored program digital computer coupled to the analog to digital converter and processing the digital output signal in response to the stored program.
Claim 40
Dependent Claim
33 words
An analog memory system as set forth in claim 11, further comprising a digital processor coupled to the analog to digital converter and processing digital data in response to the digital output signal.
Claim 41
Dependent Claim
59 words
An analog memory system as set forth in claim 11, further comprising a digital processor coupled to the analog to digital converter and processing digital data in response to the digital output signal, wherein the analog memory includes an analog writing circuit coupled to the digital to analog converter and writing the analog input signal into the analog memory.
Claim 42
Dependent Claim
152 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; a reference circuit coupled to the analog memory and generating an analog reference signal in response to the analog input signal stored by the analog memory; and a refresh circuit coupled to the analog memory and to the reference circuit and reducing amplitude degradation of the analog input signal stored by the analog memory in response to the analog reference signal.
Claim 43
Dependent Claim
152 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; a reference circuit coupled to the analog memory and generating an analog reference signal in response to the analog input signal stored by the analog memory; and a refresh circuit coupled to the analog memory and to the reference circuit and reducing amplitude degradation of the analog input signal stored by the analog memory in response to the analog reference signal.
Claim 44
Dependent Claim
170 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; an analog reference circuit generating an analog reference signal; a refresh circuit coupled to the analog memory and to the analog reference circuit and refreshing the analog input signal stored by the analog memory to reduce degradation of the analog input signal in response to the analog reference signal; and an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory.
Claim 45
Dependent Claim
170 words
An analog memory system comprising: a digital input circuit generating a digital input signal; a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal; an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; an analog reference circuit generating an analog reference signal; a refresh circuit coupled to the analog memory and to the analog reference circuit and refreshing the analog input signal stored by the analog memory to reduce degradation of the analog input signal in response to the analog reference signal; and an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory.
Claim 46
Dependent Claim
113 words
An analog memory system comprising: an analog memory storing an analog signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory; a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number; and a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number.
Claim 47
Dependent Claim
113 words
An analog memory system comprising: an analog memory storing an analog signal; a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory; an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory; a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory; a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number; and a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number.
Claim 48
Dependent Claim
116 words
An analog memory system comprising: an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; a reference circuit coupled to the analog memory and generating a reference signal in response to the analog signal stored by the analog memory; and a compensation circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the reference signal.
Claim 49
Dependent Claim
116 words
An analog memory system comprising: an analog memory coupled to the digital to analog converter and storing the analog input signal; a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory; a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory; a reference circuit coupled to the analog memory and generating a reference signal in response to the analog signal stored by the analog memory; and a compensation circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the reference signal.
References Cited (Backward Citations)
US3355719A
Cited
US3315235A
Cited
US3462742A
Cited
US3646522A
Cited
US3593313A
Cited
US3654499A
Cited
US3702988A
Cited
US4371953A
Cited
US3701125A
Cited
US3772658A
Cited
US3670313A
Cited
US3689902A
Cited
US3763480A
Cited
US3701132A
Cited
US4092734A
Cited
US3787852A
Cited
US3887762A
Cited
US4910706A
Cited
US3797002A
Cited
US3810126A
Cited
US3857101A
Cited
US3877056A
Cited
US3956624A
Cited
US3876989A
Cited
US3859640A
Cited
US3947826A
Cited
US3903543A
Cited
US3914748A
Cited
US3967263A
Cited
US3950732A
Cited
US3947827A
Cited
US3947827B1
Cited
US3991409A
Cited
US3931510A
Cited
US4322819A
Cited
US4209853A
Cited
US4523290A
Cited
US3941979A
Cited
US4034199A
Cited
US4209852A
Cited
US3958210A
Cited
US4209843A
Cited
US3986176A
Cited
US4445189A
Cited
US4318188A
Cited
US4271488A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |