US3914748A
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Isolation-element CCD serial-parallel-serial analog memory
Assignee: Texas Instruments Inc
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Filing: 1974-04-29
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Granted: 1975-10-21
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Expires: 1994-04-29
Abstract
Abstract A CCD shift register involves a serial input channel and a serial output channel interconnected by a plurality of parallel channels formed in a semiconductor body with separate arrays of multi electrode sets of phase electrodes for receiving alternately isolation element charge packets and information charge packets, overlaying the input, parallel and output channels. A summing gate electrode common to all of the parallel channels is adjacent the output channel. Control means actuates the gate to transfer charge packets from each parallel channel into the output channel and clocks the charge packets to the output. In one aspect, two shift registers are provided with means to inject time samples of an input signal alternately to the two shift registers and to multiplexing the outputs therefrom.
Inventors
- 👤 James B Barton
- 👤 Jr Tom F Cheek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:23
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04; G11C19/00; G11C19/28; G11C19/287; G11C19/34; G11C19/36; H; H10; H10D; H10D84/00; H10D84/891
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
149 words
A charge coupled shift register for handling time sampled analog information input packets comprising: a. an isolation element charge packet producing means, b. a serial input channel to receive alternately isolation element charge packets from said isolation element charge packet producing means and information packets, and a serial output channel connected to said input channel by a plurality of parallel channels wherein all said channels are formed in a semiconductor body, c. arrays of multi electrode sets of phase electrodes insulated from and overlaying said input, parallel and output channels, d. an output transfer electrode common to all of the parallel channels, e. means to actuate said transfer electrode to transfer charge packets from each parallel channel into said output channel for summation at an information and isolation element charge packet summation rate, and f. means to clock the combined charge packets to the output of said output channel.
Claim 2
Dependent Claim
149 words
A charge coupled shift register for handling time sampled analog information input packets comprising: a. an isolation element charge packet producing means, b. a serial input channel to receive alternately isolation element charge packets from said isolation element charge packet producing means and information packets, and a serial output channel connected to said input channel by a plurality of parallel channels wherein all said channels are formed in a semiconductor body, c. arrays of multi electrode sets of phase electrodes insulated from and overlaying said input, parallel and output channels, d. an output transfer electrode common to all of the parallel channels, e. means to actuate said transfer electrode to transfer charge packets from each parallel channel into said output channel for summation at an information and isolation element charge packet summation rate, and f. means to clock the combined charge packets to the output of said output channel.
Claim 3
Dependent Claim
32 words
The combination set forth in claim 1 in which said sets of electrodes include electrodes to permit separation of adjacent charge packets by intervening isolation packets while maintaining desired information output level.
Claim 4
Dependent Claim
23 words
The combination set forth in claim 1 in which multi phase voltage pulses are applied to said electrodes to transfer said charge packets.
Claim 5
Dependent Claim
34 words
The combination set forth in claim 3 in which the rate of said pulses applied to electrodes over said serial channels is high compared to the rate of pulses applied to said parallel channels.
Claim 6
Dependent Claim
29 words
The combination set forth in claim 1 in which the electrode arrays overlying said parallel channels comprise electrodes each of which is common to all of said parallel channels.
Claim 7
Dependent Claim
66 words
The combination set forth in claim 1 in which means are provided to fix said first rate such that a charge packet is shifted through two sets of said electrodes in said first and second array in each said sample interval and means are provided to detect the charge packets at said output structure with each detected packet comprising a primary bit and an isolation bit.
Claim 8
Dependent Claim
152 words
A charge coupled system comprising: a. a serial-in parallel-out charge coupled shift register defIned in a semiconductor substrate wherein each information and isolation bit of said shift register are defined by sets of spaced apart substantially parallel electrodes for alternately receiving an isolation bit and an information bit, b. a set of parallel charge coupled shift registers, one of which is coupled to each information and isolation bit location on said serial-in parallel-out shift register for transfer of bits to said parallel registers, c. a parallel-in serial-out charge coupled shift register connected to receive the information and isolation bits from said parallel shift registers, d. means to clock charges along said registers, e. a transfer electrode to transfer the information and isolation bits from said parallel registers to said parallel-in serial-out register, and f. means to sum each information bit and its isolation bit prior to transfer to said parallel-in serial-out register.
Claim 9
Dependent Claim
152 words
A charge coupled system comprising: a. a serial-in parallel-out charge coupled shift register defIned in a semiconductor substrate wherein each information and isolation bit of said shift register are defined by sets of spaced apart substantially parallel electrodes for alternately receiving an isolation bit and an information bit, b. a set of parallel charge coupled shift registers, one of which is coupled to each information and isolation bit location on said serial-in parallel-out shift register for transfer of bits to said parallel registers, c. a parallel-in serial-out charge coupled shift register connected to receive the information and isolation bits from said parallel shift registers, d. means to clock charges along said registers, e. a transfer electrode to transfer the information and isolation bits from said parallel registers to said parallel-in serial-out register, and f. means to sum each information bit and its isolation bit prior to transfer to said parallel-in serial-out register.
Claim 10
Dependent Claim
124 words
A charge coupled system comprising: a. a serial-in parallel-out charge coupled shift register defined in a semiconductor substrate, each element of said shift register defined by sets of spaced apart substantially parallel electrodes for receiving alternately isolation bits and information bits separated from adjacent elements by sets of like electrodes through which the isolation and information bits are passed, b. a parallel-in serial-out charge coupled shift register connected to receive the bits from said parallel shift registers, c. a transfer electrode for shifting the bits from said parallel registers to said parallel-in serial-out register, and d. a summing electrode adjacent said transfer electrode to sum each information bit and its isolation bit prior to transfer by said transfer electrode to said parallel-in serial-out register.
Claim 11
Dependent Claim
124 words
A charge coupled system comprising: a. a serial-in parallel-out charge coupled shift register defined in a semiconductor substrate, each element of said shift register defined by sets of spaced apart substantially parallel electrodes for receiving alternately isolation bits and information bits separated from adjacent elements by sets of like electrodes through which the isolation and information bits are passed, b. a parallel-in serial-out charge coupled shift register connected to receive the bits from said parallel shift registers, c. a transfer electrode for shifting the bits from said parallel registers to said parallel-in serial-out register, and d. a summing electrode adjacent said transfer electrode to sum each information bit and its isolation bit prior to transfer by said transfer electrode to said parallel-in serial-out register.
Claim 12
Dependent Claim
18 words
The combination set forth in claim 8 in which said system is formed on a single semiconductor body.
Claim 13
Dependent Claim
29 words
The combination set forth in claim 8 in which said registers are surface registers covered by an insulating layer on top of which said sets of electrodes are formed.
Claim 14
Dependent Claim
60 words
The combination set forth in claim 8 in which a first clock pulse source is connected to transfer charges along said parallel shift registers and a second clock pulse source is provided to shift charges along said serial shift registers at a rate higher than in said parallel shift registers in proportion to the number of said parallel shift registers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-20 | 1979-04-21 | 1979-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-20 | 1983-04-21 | 1983-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-20 | 1987-04-21 | 1987-10-21 | $7700.00 | Window Closed / Lapsed |