US4322819A
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Memory system having servo compensation
Assignee: Individual
•
Filing: 1978-03-23
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Granted: 1982-03-30
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Expires: 1998-03-23
Abstract
Abstract The present invention is directed to a servo system for compensation of memory signals. In a preferred embodiment, the memory system is a CCD analog read only memory system. In alternate embodiments, the memory system may include an alterable memory, a bubble memory, and/or other memories. Adaptive servo compensation is provided by storing reference signals and compensating stored information signals with the stored reference signals using a compensation servo arrangement. The servo may be an implicit servo for compensating signal amplitude such as to correct charge transfer errors in a CCD memory.
Inventors
- 👤 Gilbert P. Hyatt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:02
CPC Classifications
B; B60; B60R; B60R16/00; B60R16/02; B60R16/037; B60R16/0373; F; F21; F21V; F21V23/00; G; G01; G01S; G01S15/00; G01S15/88; G01S15/89; G01S15/8906; G01S15/8965; G01S15/897; G01S15/8977; G01S7/00; G01S7/52; G01S7/52017; G01S7/52023; G01S7/52025; G01S7/52026; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/13306; G02F1/13318; G03; G03F; G03F9/00; G03F9/70; G03F9/7049; G03F9/7088; G04; G04G; G04G99/00; G04G99/006; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/19; G05B19/33; G05B19/35; G05B19/351; G05B19/408; G05B19/4083; G05B19/4086; G05B19/409; G05B19/4093; G05B19/414; G05B19/4142; G06; G06J; G06J1/00; G07; G07G; G07G1/00; G07G1/12; G10; G10L; G10L19/00; G11; G11C; G11C11/00; G11C11/56; G11C11/565; G11C19/00; G11C19/28; G11C19/287; G11C19/34; G11C19/36; G11C27/00; G11C27/04; G11C7/00; G11C7/10; G11C7/1015; G11C7/1042; G11C13/00; G11C13/04; G11C7/16; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
95 words
A memory system comprising: an analog memory for storing analog signals; an input circuit for storing the analog signals in said analog memory at a first data rate; an output circuit for outputting the analog signals from said analog memory at a second data rate that is lower than said first data rate; a servo for generating refreshed output analog signals in response to the analog signals output with said output circuit; and an analog to digital converter for generating digital output signals in response to the refreshed output analog signals generated with said servo.
Claim 2
Dependent Claim
95 words
A memory system comprising: an analog memory for storing analog signals; an input circuit for storing the analog signals in said analog memory at a first data rate; an output circuit for outputting the analog signals from said analog memory at a second data rate that is lower than said first data rate; a servo for generating refreshed output analog signals in response to the analog signals output with said output circuit; and an analog to digital converter for generating digital output signals in response to the refreshed output analog signals generated with said servo.
Claim 3
Dependent Claim
23 words
The system as set forth in claim 1 above, wherein said memory includes means for storing the analog signals as analog magnetic signals.
Claim 4
Dependent Claim
23 words
The system as set forth in claim 1 above, wherein said servo includes means for generating the refreshed signals as a digital signal.
Claim 5
Dependent Claim
23 words
The system as set forth in claim 1 above, wherein said memory includes means for storing the analog signals as acoustical analog signals.
Claim 6
Dependent Claim
84 words
The system as set forth in claim 1 above, wherein said analog memory includes a charge coupled device for storing the analog signals; said charge coupled device including a clock circuit for shifting the analog signals, wherein said clock circuit includes means for shifting the analog signals stored in said analog memory at the first data rate for storing the analog signals and means for shifting the analog signals stored in said analog memory at the second data rate for outputting the analog signals.
Claim 7
Dependent Claim
30 words
The system as set forth in claim 1 above, wherein said servo includes a digital to analog converter for correcting a scale factor related error in the stored analog signals.
Claim 8
Dependent Claim
28 words
The system as set forth in claim 6 above, wherein said servo further includes means for providing bias compensation to reduce bias related errors in said refreshed signal.
Claim 9
Dependent Claim
45 words
The system as set forth in claim 1 above, wherein said servo includes a comparator for generating a comparison signal related to a comparison between a reference signal and the stored analog signals; said system further comprising a digital computer for generating the reference signal.
Claim 10
Dependent Claim
48 words
The system as set forth in claim 1 above, wherein said servo includes scale factor means for generating a scale factor compensated signal in response to the stored analog signals and bias means for generating a bias compensated refreshed signal in response to the scale factor compensated signal.
Claim 11
Dependent Claim
46 words
The system as set forth in claim 1 above, wherein said servo includes bias means for generating a bias compensated signal in response to the stored analog signals and scale factor means for generating a scale factor compensated signal in response to the bias compensated signal.
Claim 12
Dependent Claim
25 words
The system as set forth in claim 1 above, further comprising a plurality of said servos distributed at a plurality of locations in said memory.
Claim 13
Dependent Claim
29 words
The system as set forth in claim 1 above, wherein said servo includes means for generating the refreshed signals having a reduced non-linearality in response to the stored signals.
Claim 14
Dependent Claim
39 words
The system as set forth in claim 1 above, wherein said servo includes an implicit servo for generating an inverse function, wherein said implicit servo includes means for compensating the refreshed signal in response to the stored electrical signals.
Claim 15
Dependent Claim
25 words
The system as set forth in claim 1 above, further comprising monolithic means for combining said memory and said servo on a common monolithic structure.
Claim 16
Dependent Claim
22 words
The system as set forth in claim 1 above, wherein said servo includes means for compensating at least three types of errors.
Claim 17
Dependent Claim
28 words
The system as set forth in claim 15 above, wherein two of said at least three types of errors are a bias error and a scale factor error.
Claim 18
Dependent Claim
21 words
The system as set forth in claim 1 above, wherein said servo includes means for controlling gain of an electronic circuit.
Claim 19
Dependent Claim
34 words
The system as set forth in claim 1 above, wherein said servo includes gain control means for controlling scale factor of the refreshed signal and bias means for controlling bias of the refreshed signal.
Claim 20
Dependent Claim
18 words
The system as set forth in claim 1 above, wherein said memory includes an analog read only memory.
Claim 21
Dependent Claim
61 words
A memory system comprising: a memory for storing signals and a plurality of servos for refreshing the signals stored in said memory, wherein said plurality of servos includes a first plurality of bias refresh circuits for bias compensating signals stored in said memory and a second plurality of scale factor refresh circuits for scale factor compensating signals stored in said memory.
Claim 22
Dependent Claim
61 words
A memory system comprising: a memory for storing signals and a plurality of servos for refreshing the signals stored in said memory, wherein said plurality of servos includes a first plurality of bias refresh circuits for bias compensating signals stored in said memory and a second plurality of scale factor refresh circuits for scale factor compensating signals stored in said memory.
Claim 23
Dependent Claim
21 words
The system as set forth in claim 20 above, where the first plurality represents a greater quantity than the second plurality.
Claim 24
Dependent Claim
21 words
The system as set forth in claim 20 above, wherein the second plurality represents a greater quantity than the first plurality.
Claim 25
Dependent Claim
59 words
A memory system comprising: a digital computer for processing digital information; a digital to analog converter for generating an analog information signal in response to digital information processed with said digital computer; an analog memory for storing analog information generated with said digital to analog converter; and a servo for refreshing the analog information stored in said analog memory.
Claim 26
Dependent Claim
59 words
A memory system comprising: a digital computer for processing digital information; a digital to analog converter for generating an analog information signal in response to digital information processed with said digital computer; an analog memory for storing analog information generated with said digital to analog converter; and a servo for refreshing the analog information stored in said analog memory.
Claim 27
Dependent Claim
38 words
A reverberation system comprising: a memory for storing electrical signals; a servo for generating a refreshed signal in response to electrical signals stored in said memory; and reverberation means for providing reverberation in response to the refreshed signal.
Claim 28
Dependent Claim
38 words
A reverberation system comprising: a memory for storing electrical signals; a servo for generating a refreshed signal in response to electrical signals stored in said memory; and reverberation means for providing reverberation in response to the refreshed signal.
Claim 29
Dependent Claim
58 words
A memory system comprising: a memory for storing electrical signals and a servo for generating a refreshed signal in response to electrical signals stored in said memory, wherein said servo includes a differential circuit for providing a differential signal in response to an electrical signal stored in said memory to generate a refreshed signal having reduced differential error.
Claim 30
Dependent Claim
58 words
A memory system comprising: a memory for storing electrical signals and a servo for generating a refreshed signal in response to electrical signals stored in said memory, wherein said servo includes a differential circuit for providing a differential signal in response to an electrical signal stored in said memory to generate a refreshed signal having reduced differential error.
Claim 31
Dependent Claim
101 words
A memory system comprising: an analog memory for storing analog signals; an analog refresh circuit for refreshing the analog signals stored in said analog memory at a refresh rate; an analog output circuit for outputting the analog signals stored in said analog memory at an output rate; and a rate circuit for controlling signal rates; wherein said rate circuit includes a. refresh rate means for generating a refresh rate to control said analog refresh circuit and b. output rate means for generating an output rate to control said analog output circuit, wherein the refresh rate is different from the output rate.
Claim 32
Dependent Claim
101 words
A memory system comprising: an analog memory for storing analog signals; an analog refresh circuit for refreshing the analog signals stored in said analog memory at a refresh rate; an analog output circuit for outputting the analog signals stored in said analog memory at an output rate; and a rate circuit for controlling signal rates; wherein said rate circuit includes a. refresh rate means for generating a refresh rate to control said analog refresh circuit and b. output rate means for generating an output rate to control said analog output circuit, wherein the refresh rate is different from the output rate.
Claim 33
Dependent Claim
24 words
The system as set forth in claim 24 above, wherein said rate means includes means for providing a higher refresh rate than output rate.
Claim 34
Dependent Claim
67 words
A memory system comprising: an analog memory for storing analog signals; a refresh circuit for refreshing the analog signals stored in said analog memory, wherein said refresh circuit includes a differential amplifier for bias refreshing the analog signals stored in said analog memory and a transistor connected in a common leg of said differential amplifier for scale factor refreshing the analog signals stored in said analog memory.
Claim 35
Dependent Claim
67 words
A memory system comprising: an analog memory for storing analog signals; a refresh circuit for refreshing the analog signals stored in said analog memory, wherein said refresh circuit includes a differential amplifier for bias refreshing the analog signals stored in said analog memory and a transistor connected in a common leg of said differential amplifier for scale factor refreshing the analog signals stored in said analog memory.
Claim 36
Dependent Claim
44 words
A memory system comprising: a memory for storing signals; a reference circuit for generating a reference signal; a comparator for generating a comparison signal in response to a comparison of the stored signals from said memory and the reference signal from said reference circuit.
Claim 37
Dependent Claim
44 words
A memory system comprising: a memory for storing signals; a reference circuit for generating a reference signal; a comparator for generating a comparison signal in response to a comparison of the stored signals from said memory and the reference signal from said reference circuit.
Claim 38
Dependent Claim
27 words
The system as set forth in claim 29 above, wherein said comparator means includes an impliit servo for providing compensation of the signals stored in said memory.
Claim 39
Dependent Claim
103 words
The system as set forth in claim 29 above, wherein said memory is an analog CCD read only memory for storing the signals as analog charge signals in read only memory form, wherein said reference circuit includes means for generating the reference signal as an analog reference signal related to a desired signal in said memory; and wherein said comparison means includes an analog comparator for generating the comparison signal as an analog comparison signal in response to a comparison of the analog reference signal from said reference signal generating means and at least one of the analog signals stored in said memory.
Claim 40
Dependent Claim
59 words
An analog memory system comprising: reference input means for generating an analog reference signal; memory storing means for storing an analog signal; and memory output means for generating an analog memory output signal in response to a comparison between the analog signal stored in said memory storing means and the analog reference signal generated with said reference input means.
Claim 41
Dependent Claim
59 words
An analog memory system comprising: reference input means for generating an analog reference signal; memory storing means for storing an analog signal; and memory output means for generating an analog memory output signal in response to a comparison between the analog signal stored in said memory storing means and the analog reference signal generated with said reference input means.
Claim 42
Dependent Claim
86 words
A memory system comprising: an analog memory for storing analog signals a reference circuit for generating a reference signal; a comparator for comparing the analog signals stored in said analog memory with the reference signal generated with said reference circuit; and an analog to digital converter for converting analog signals stored in said analog memory to digital output signals in response to a comparison between the analog signals stored in said analog memory and the reference signal generated with said reference circuit determined by said comparator.
Claim 43
Dependent Claim
86 words
A memory system comprising: an analog memory for storing analog signals a reference circuit for generating a reference signal; a comparator for comparing the analog signals stored in said analog memory with the reference signal generated with said reference circuit; and an analog to digital converter for converting analog signals stored in said analog memory to digital output signals in response to a comparison between the analog signals stored in said analog memory and the reference signal generated with said reference circuit determined by said comparator.
Claim 44
Dependent Claim
18 words
The system as set forth in claim 33 above, wherein said memory includes an analog read only memory.
Claim 45
Dependent Claim
105 words
A memory system for storing electrical signals; said memory system comprising: memory means for storing a plurality of analog signals as stored electrical analog signals; shifting means for shifting the stored electrical analog signals; analog data refresh means for processing the electrical analog signals from said shifting means, said analog data refresh means including reference means for generating an analog reference signals and a servo for processing the electrical analog signals from said shifting means in response to the analog reference signals and analog-to-digital converter means for generating digital output signals in response to the processed electrical analog signals from said analog data refresh means.
Claim 46
Dependent Claim
105 words
A memory system for storing electrical signals; said memory system comprising: memory means for storing a plurality of analog signals as stored electrical analog signals; shifting means for shifting the stored electrical analog signals; analog data refresh means for processing the electrical analog signals from said shifting means, said analog data refresh means including reference means for generating an analog reference signals and a servo for processing the electrical analog signals from said shifting means in response to the analog reference signals and analog-to-digital converter means for generating digital output signals in response to the processed electrical analog signals from said analog data refresh means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-03-29 | 1985-09-28 | 1986-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-03-29 | 1989-09-28 | 1990-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-03-29 | 1993-09-28 | 1994-03-30 | $7700.00 | Window Closed / Lapsed |