System for compensating voltage for a CCD sensing circuit

Claim 3

The apparatus defined by claim 1 wherein said output of said sensor is a function of the relative magnitudes of said register reference output signal and said regulated output potential.

Claim 4

In a CCD memory system disposed on a substrate employing at least one sensing transistor for sensing the output of a storage shift register, an improvement for generating a reference potential for said sensing transistor comprising: a shift register having the same general geometry as said storage shift register, disposed on said substrate; and voltage generation means for generating said reference potential, said generation means being controlled, at least in part, by said shift register; whereby said improvement compensates for parameter variations on said substrate.

Claim 5

In a CCD memory system disposed on a substrate employing at least one sensing transistor for sensing the output of a storage shift register, an improvement for generating a reference potential for said sensing transistor comprising: a shift register having the same general geometry as said storage shift register, disposed on said substrate; and voltage generation means for generating said reference potential, said generation means being controlled, at least in part, by said shift register; whereby said improvement compensates for parameter variations on said substrate.

Claim 6

The improvement defined by claim 3 wherein a predetermined signal is applied to said shift register by a signal generator disposed on said substrate.

Claim 7

In a circuit for sensing the output charge from a charge-coupled storage shift register which includes a sensing node for receiving said output charge, an improvement for adjusting said output charge on said sensing node as a function of non-programmed variations in the magnitude of said charge where said circuit and said shift register are disposed on a common substrate comprising: a reference shift register disposed on said common substrate; signal generation means for generating an input signal for said reference shift register coupled to said reference shift register; voltage generation means for generating an adjustment signal; and comparator means for comparing the output of said reference shift register with said adjustment signal and for controlling said voltage generation means, coupled to said reference shift register and said voltage generation means; whereby said adjustment signal may be used to adjust said output charge on said sensing node thereby providing improved sensing of charge from said storage shift register.

Claim 8

In a circuit for sensing the output charge from a charge-coupled storage shift register which includes a sensing node for receiving said output charge, an improvement for adjusting said output charge on said sensing node as a function of non-programmed variations in the magnitude of said charge where said circuit and said shift register are disposed on a common substrate comprising: a reference shift register disposed on said common substrate; signal generation means for generating an input signal for said reference shift register coupled to said reference shift register; voltage generation means for generating an adjustment signal; and comparator means for comparing the output of said reference shift register with said adjustment signal and for controlling said voltage generation means, coupled to said reference shift register and said voltage generation means; whereby said adjustment signal may be used to adjust said output charge on said sensing node thereby providing improved sensing of charge from said storage shift register.

Claim 9

The improvement defined by claim 5 wherein said reference shift register has the same general geometry as said storage shift register.

Claim 10

The improvement defined by claim 6 wherein said reference shift register includes two spaced apart, parallel channels and said storage shift register includes four spaced apart, parallel channels.

Claim 11

The improvement defined by claim 7 wherein said signal generation means generates a series of signals representing a first binary state for one of said reference registers and a series of signals representing a second binary state for the other of said reference registers.

Claim 12

The improvement defined by claim 8 including an interconnecting channel disposed between said two channels of said reference shift register.

Claim 13

In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors for sensing the output of said storage shift registers, a system for generating a reference potential which is coupled to said sensing transistors comprising: at least one generation means for generating a signal representative of a binary state; at least one reference register coupled to said generation means, said reference register having at least one channel of approximately the same length and width as a channel of said storage shift register; a reference sensing transistor having the same general characteristics as said sensing transistors, said reference sensing transistor having its gate coupled to the output of said reference register and also having its gate selectively coupled to said reference potential, said reference sensing transistor having an output control signal line; an output transistor for controlling said reference potential, said output transistor having a gate; a first current source coupled to said gate of said output transistor; a variable current source coupled to said gate of said output transistor, said variable current source being coupled to said output control signal line of said reference sensing transistor; whereby said reference potential will vary as a function of the output of said reference register and as a function of variations in said reference sensing transistor.

Claim 14

In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors for sensing the output of said storage shift registers, a system for generating a reference potential which is coupled to said sensing transistors comprising: at least one generation means for generating a signal representative of a binary state; at least one reference register coupled to said generation means, said reference register having at least one channel of approximately the same length and width as a channel of said storage shift register; a reference sensing transistor having the same general characteristics as said sensing transistors, said reference sensing transistor having its gate coupled to the output of said reference register and also having its gate selectively coupled to said reference potential, said reference sensing transistor having an output control signal line; an output transistor for controlling said reference potential, said output transistor having a gate; a first current source coupled to said gate of said output transistor; a variable current source coupled to said gate of said output transistor, said variable current source being coupled to said output control signal line of said reference sensing transistor; whereby said reference potential will vary as a function of the output of said reference register and as a function of variations in said reference sensing transistor.

Claim 15

In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors, a system for generating a reference potential coupled to said sensing transistors comprising; a register having a first and a second channel, each of said channels being of approximately the same length and width as a channel of said storage registers; a first generation means for generating a charge representing a first binary state, coupled to said first channel; a second generation means for generating a charge representing a second binary state coupled to said second channel; a cross channel interconnecting said first and second channels; a transistor for providing a control signal having its gate coupled to the output of said register, said gate being selectively coupled to said reference potential; an output transistor for controlling said reference potential, said output transistor including a gate; a first current source including a channel coupled to said gate of said output transistor; and a second current source including a channel coupled to said gate of said output transistor, said second current source being controlled by said control signal of said transistor; whereby the output of said output transistor may be used by said sensing transistor in sensing of charge from said storage shift registers.

Claim 16

In a charge-coupled memory employing a plurality of storage shift registers and a plurality of sensing transistors, a system for generating a reference potential coupled to said sensing transistors comprising; a register having a first and a second channel, each of said channels being of approximately the same length and width as a channel of said storage registers; a first generation means for generating a charge representing a first binary state, coupled to said first channel; a second generation means for generating a charge representing a second binary state coupled to said second channel; a cross channel interconnecting said first and second channels; a transistor for providing a control signal having its gate coupled to the output of said register, said gate being selectively coupled to said reference potential; an output transistor for controlling said reference potential, said output transistor including a gate; a first current source including a channel coupled to said gate of said output transistor; and a second current source including a channel coupled to said gate of said output transistor, said second current source being controlled by said control signal of said transistor; whereby the output of said output transistor may be used by said sensing transistor in sensing of charge from said storage shift registers.

Claim 17

The system defined by claim 11 wherein a capacitor is coupled to the gate of said output transistor.

Claim 18

The system defined by claim 12 wherein a bleeder circuit is coupled to the output of said output transistor.

Claim 19

The system defined in claim 13 wherein said memory and said system are disposed on a common substrate.

Claim 20

The system defined in claim 14 wherein the channels of said storage shift registers, said channels of said register and said channels of said current sources are n-channels.