US3848236A
Expired / Lapsed
US
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Threshold circuit
Assignee: Boeing North American Inc
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Filing: 1973-05-11
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Granted: 1974-11-12
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Expires: 1993-05-11
Abstract
Abstract A threshold circuit for reducing the time required to discharge an input voltage at a data node from a first to a second logic level. The circuit includes a controllable shunt field effect transistor connected to provide a secondary discharge path between the data node and a voltage reference of the second logic level. As the input voltage begins to discharge along a primary discharge path, the resulting change in the input voltage level is fed back to the control electrode of the shunt transistor to turn on the shunt transistor and connect the data node to the voltage reference along the secondary discharge path to more quickly discharge the input voltage to the second logic level. In the preferred embodiment, the threshold circuit is connected to the output node of a read-only memory to reduce the read-out time of logic information stored in the memory.
Inventors
- 👤 B Troutman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:16
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
242 words
In a semiconductor memory system including a memory having address locations for storage of binary information thereat, and means for retrieving information from a desired address location for readout at a data node by precharging said data node to a first voltage level during a precharge interval and discharging said data node to a second voltage level along a primary discharge path through said memory during an evaluation interval as a function of the binary state of information stored at said desired address location, the improvement comprising: shunt means providing a controlled, secondary discharge path for speeding the discharge of said data node, said shunt means including a shunt field effect transistor having the sourcedrain path thereof connected between said data node and a voltage source and having a control electrode connected to receive a control voltage in response to the discharging of said data node, said control voltage serving to turn on said shunt field effect transistor to complete said secondary discharge path and thereby decrease the time required to discharge said data node; and wherein said voltage source connected to said shunt field effect transistor is a clock voltage source which assumes said first voltage level during said precharge interval and assumes said second voltage level during said evaluation interval, whereby said voltage source, if said shunt field effect transistor is conductive during said precharge interval, prevents premature discharge of said data node while contributing to the actual precharge thereof.
Claim 2
Dependent Claim
242 words
In a semiconductor memory system including a memory having address locations for storage of binary information thereat, and means for retrieving information from a desired address location for readout at a data node by precharging said data node to a first voltage level during a precharge interval and discharging said data node to a second voltage level along a primary discharge path through said memory during an evaluation interval as a function of the binary state of information stored at said desired address location, the improvement comprising: shunt means providing a controlled, secondary discharge path for speeding the discharge of said data node, said shunt means including a shunt field effect transistor having the sourcedrain path thereof connected between said data node and a voltage source and having a control electrode connected to receive a control voltage in response to the discharging of said data node, said control voltage serving to turn on said shunt field effect transistor to complete said secondary discharge path and thereby decrease the time required to discharge said data node; and wherein said voltage source connected to said shunt field effect transistor is a clock voltage source which assumes said first voltage level during said precharge interval and assumes said second voltage level during said evaluation interval, whereby said voltage source, if said shunt field effect transistor is conductive during said precharge interval, prevents premature discharge of said data node while contributing to the actual precharge thereof.
Claim 3
Dependent Claim
41 words
The memory system of claim 1 including: an output node; an inverter circuit connected between said data node and said output node, and means connecting said output node in feedback relation to the control electrode of said shunt field effect transistor.
References Cited (Backward Citations)
US3765002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-11 | 1978-05-13 | 1978-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-11 | 1982-05-13 | 1982-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-11 | 1986-05-13 | 1986-11-12 | $7700.00 | Window Closed / Lapsed |