US3958210A
Expired / Lapsed
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Charge coupled device systems
Assignee: RCA Corp
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Filing: 1975-02-05
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Granted: 1976-05-18
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Expires: 1995-02-05
Abstract
Abstract Analog signals initially are stored in an a linear array such as a charge coupled device (CCD) register. There is provided, for each stage of the linear array, a different column of a CCD matrix, termed here a B register. During a transfer interval, the analog charge signals concurrently are permitted to flow into the columns. As the stages in the B register have much smaller charge storage capacity than the stages in the linear array, the charge signal fills and then overflows successive potential wells of each column until an equilibrium condition is reached. At equilibrium, the number of filled wells in a column will be proportional to the amplitude of the charge signal supplied to that column by the stage of the linear array coupled to the column. The matrix is read by concurrently sensing all of the signals present in one column, and then doing the same for each following column.
Inventors
- 👤 Peter Alan Levine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:34
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/15; H10F39/152; G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/287; G11C19/34; G11C19/36; H04; H04N; H04N25/00; H04N25/70; H04N25/701; H10D; H10D84/00; H10D84/891; H03; H03M; H03M1/00; H03M1/12; H03M1/34
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
187 words
In combination: an input linear array having a plurality of stages, each capable of storing a given amount of charge, each stage for storing an analog charge signal; a plurality n of conversion charge coupled device registers, each conversion register having a plurality of at least m stages and each stage having only a fraction of the storage capacity of a stage of said input linear array, where n and m are integers greater than 1; means for flowing the charge signal in each j'th stage of said input linear array into from 0 to n of the j'th stages of said conversion registers, the number depending on the amplitude of the charge signal present in the j'th stage of the input linear array, where j is an integer equal to 1, 2 - - - m, m being not greater than the total number of stages in the input linear array; means for concurrently shifting the charge signals in said n conversion registers down said registers; and means for reading, in parallel, each group of charge signals reaching the output stage of said n conversion registers.
Claim 2
Dependent Claim
187 words
In combination: an input linear array having a plurality of stages, each capable of storing a given amount of charge, each stage for storing an analog charge signal; a plurality n of conversion charge coupled device registers, each conversion register having a plurality of at least m stages and each stage having only a fraction of the storage capacity of a stage of said input linear array, where n and m are integers greater than 1; means for flowing the charge signal in each j'th stage of said input linear array into from 0 to n of the j'th stages of said conversion registers, the number depending on the amplitude of the charge signal present in the j'th stage of the input linear array, where j is an integer equal to 1, 2 - - - m, m being not greater than the total number of stages in the input linear array; means for concurrently shifting the charge signals in said n conversion registers down said registers; and means for reading, in parallel, each group of charge signals reaching the output stage of said n conversion registers.
Claim 3
Dependent Claim
104 words
In the combination as set forth in claim 1, said conversion registers being integrated onto a common semiconductor substrate and each register being separated from the next adjacent register by means providing a potential barrier in the substrate which is sufficiently low to permit charge signal to pass from a stage in one register to a corresponding stage in the next register during the flowing of charge from said input linear array to said conversion registers, and which is sufficiently high to isolate the charge in one register from that in the next adjacent register, during the propagation of charge down said conversion registers.
Claim 4
Dependent Claim
16 words
In the combination as set forth in claim 2, said linear array comprising a charge-coupled register.
Claim 5
Dependent Claim
17 words
In the combination as set forth in claim 2, said linear array comprising a radiation sensing array.
Claim 6
Dependent Claim
35 words
In the combination as set forth in claim 2, said means providing a potential barrier comprising a diffusion in said substrate of the same conductivity as the substrate but more highly doped than the substrate.
Claim 7
Dependent Claim
53 words
In the combination as set forth in claim 1, each conversion register including an output stage at one end of the register and an input stage at the other end of the register, and further including n feedback connections, each connecting an output stage of a conversion register back to its input stage.
Claim 8
Dependent Claim
100 words
In combination: a charge coupled device array comprising a substrate, a plurality of channels in the substrate extending in the row direction, and electrodes to which transfer voltages may be applied, insulated from the substrate and extending in the column direction; means for transferring charge signals into said array comprising means for flowing said signals into the array in the column direction for passage from channel-to-channel along the columns; and means for reading charge signals out of said array comprising means for applying transfer voltages to said electrodes for shifting said charge signals in the row direction along said rows.
Claim 9
Dependent Claim
100 words
In combination: a charge coupled device array comprising a substrate, a plurality of channels in the substrate extending in the row direction, and electrodes to which transfer voltages may be applied, insulated from the substrate and extending in the column direction; means for transferring charge signals into said array comprising means for flowing said signals into the array in the column direction for passage from channel-to-channel along the columns; and means for reading charge signals out of said array comprising means for applying transfer voltages to said electrodes for shifting said charge signals in the row direction along said rows.
Claim 10
Dependent Claim
44 words
In the combination as set forth in claim 7, said means for transferring charge signals into said array comprising a radiation sensing array, and charge transfer means for transferring the charge signals accumulated in said radiation sensing array into said charge coupled device array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-18 | 1979-11-17 | 1980-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-18 | 1983-11-17 | 1984-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-18 | 1987-11-17 | 1988-05-18 | $7700.00 | Window Closed / Lapsed |