Information storage devices

Claim 2

IN A CHARGE TRANSFER APPARATUS OF THE TYPE FOR STORAGE AND SERIAL TRANSFER OF CHARGE CARRIERS LOCALIZED IN A PLURALITY OF INDUCED POTENTIAL ENERGY MINIMA ALONG A PORTION OF A SEMICONDUCTOR CHARGE STORAGE MEDIUM BY SEQUENTIALLY APPLYING DIFFERENT POTENTIALS TO SUCCESSIVE PORTIONS OF THE SURFACE OF THE MEDIUM THROUGH A PLURALITY OF ELECTRODES, THE INVENTION CHARACTERIZED IN THAT THE CHARGE STORAGE MEDIUM IS OF A SINGLE CONDUCTIVITY TYPE.

Claim 3

In a charge transfer apparatus of the type for storage and serial transfer of charge carriers localized in a plurality of induced potential energy minima along a portion of a semiconductor charge storage medium by sequentially applying different potentials to successive portions of the surface of the medium through a plurality of electrodes, the invention characterized in that the portion of the charge storage medium in which charges are stored and transferred and which directly underlies each electrode of said plurality of electrodes is of a single conductivity type.

Claim 4

In a charge transfer apparatus of the type for storage and serial transfer of charge carriers localized in a plurality of induced potential energy minima along a portion of a semiconductor charge storage medium by sequentially applying different potentials to successive portions of the surface of the medium through a plurality of electrodes, the invention characterized in that the portion of the charge storage medium in which charges are stored and transferred and which directly underlies each electrode of said plurality of electrodes is of a single conductivity type.

Claim 5

The apparatus of claim 2 in which the charge storage medium is covered with an insulating layer and the plurality of electrodes are disposed on the insulating layer.

Claim 6

The apparatus of claim 3 in which the charge storage medium is silicon.

Claim 7

The apparatus of claim 3 in which the insulating layer comprises SiO2.

Claim 8

The apparatus of claim 2 including means for exposing the device to light in order to form the charge carriers.

Claim 9

The apparatus of claim 6 in which charge carriers are formed simultaneously in a plurality of potential energy minima.

Claim 10

The apparatus of claim 2 further including a piezoelectric layer formed on one surface of the device with means for creating an acoustic wave in the layer so that an electrical field is created by the acoustic wave propagating in the piezoelectric layer.

Claim 11

The apparatus of claim 2 in which the portion of the charge storage medium in which charges are stored and transferred is a surface portion.

Claim 12

A charge coupled device comprising a charge storage medium, a charge input region at a first location in the charge storage medium at which charge carriers representing signal information can be introduced into the medium, a charge detection region at a second location in the charge storage medium at which charge carriers can be detected and a charge storage and transfer channel interconnecting the input region and the detection region, the charge storage and transfer channel consisting of a single conductivity type semiconductor, an insulating layer overlying the charge storage medium, and at least four discrete electrodes disposed on the insulating layer overlying the charge storage and transfer channel.

Claim 13

A charge coupled device comprising a charge storage medium, a charge input region at a first location in the charge storage medium at which charge carriers representing signal information can be introduced into the medium, a charge detection region at a second location in the charge storage medium at which charge carriers can be detected and a charge storage and transfer channel interconnecting the input region and the detection region, the charge storage and transfer channel consisting of a single conductivity type semiconductor, an insulating layer overlying the charge storage medium, and at least four discrete electrodes disposed on the insulating layer overlying the charge storage and transfer channel.

Claim 14

The device of claim 10 in which the charge input region for introducing charge carriers comprises a p-n junction.

Claim 15

The device of claim 10 in which the charge Input region for introducing charge carriers comprises a metal-insulator-semiconductor device.

Claim 16

A semiconductive device comprising a semiconductive charge storage layer having a major surface, an insulating layer overlying said major surface, an electrode assembly on the insulating layer including a plurality of electrodes, means for forming a succession of spaced storage sites for the storage of charge carriers in the charge storage layer and for transferring stored charge carriers between successive sites in a predetermined direction, and wherein the charge storage and transfer layer consists of a material that is of a single conductivity type.

Claim 17

A semiconductive device comprising a semiconductive charge storage layer having a major surface, an insulating layer overlying said major surface, an electrode assembly on the insulating layer including a plurality of electrodes, means for forming a succession of spaced storage sites for the storage of charge carriers in the charge storage layer and for transferring stored charge carriers between successive sites in a predetermined direction, and wherein the charge storage and transfer layer consists of a material that is of a single conductivity type.

Claim 18

A semiconductive device comprising a semiconductive charge layer having a major surface, an insulating layer overlying said major surface, an electrode assembly on the insulating layer including a plurality of electrodes, means for forming a succession of spaced storage sites for the storage of charge carriers in the charge storage layer and for transferring stored charge carriers between successive sites in a predetermined direction, and wherein the portion of the charge storage and transfer layer that directly underlies each electrode is of a single conductivity type.

Claim 19

A semiconductive device comprising a semiconductive charge layer having a major surface, an insulating layer overlying said major surface, an electrode assembly on the insulating layer including a plurality of electrodes, means for forming a succession of spaced storage sites for the storage of charge carriers in the charge storage layer and for transferring stored charge carriers between successive sites in a predetermined direction, and wherein the portion of the charge storage and transfer layer that directly underlies each electrode is of a single conductivity type.

Claim 20

The device of claim 14 further including three separate conductors each connected to a different one of every third electrode of the plurality of electrodes.

Claim 21

The device of claim 15 in which the electrodes are shaped and placed so that the three separate conductors extend parallel to one another.

Claim 22

The device of claim 14 in which the means for forming a succession of spaced storage sites includes circuit means connected to the plurality of electrodes for applying pulses sequentially to each of the plurality of electrodes.

Claim 23

The device of claim 17 in which the pulses are square wave pulses.

Claim 24

The device of claim 17 in which the pulses are sine wave pulses.

Claim 25

The device of claim 17 in which the pulses are sawtooth pulses.

Claim 26

The device of claim 14 including electrical circuit means for biasing all of the electrodes at a uniform potential so that the surface of the semiconductive charge storage layer can be maintained depleted during operation of the device.

Claim 27

The device of claim 14 in which the space between each of the plurality of electrodes is approximately 3 microns.

Claim 28

The device of claim 14 in which the length of each of the plurality of electrodes as measured in the predetermined direction is comparable to or less than the thickness of the insulating layer.

Claim 29

The device of claim 14 including charge detection means at a charge detection region for detecting the presence, absence or amount of charge in the charge detection region.

Claim 30

The device of claim 24 in which the charge detection means comprises a metal-insulator-semiconductor device.

Claim 31

The device of claim 25 in which the metal-insulator-semiconductor device is connected to the gate of a field-effect transistor for measuring the capacitance of the metal-insulator-semiconductor device.

Claim 32

The device of claim 24 in which the charge detection means is coupled to a charge input means to recirculate charge.

Claim 33

The device of claim 24 including means for regenerating the charge detected by the charge detection means.

Claim 34

The device of claim 24 in which the charge detection means comprises a capacitive bridge circuit electrically coupled to the charge detection region for measuring changes in the capacitance of the charge detection region.

Claim 35

The device of claim 24 in which the charge detection means comprises two adjacent electrodes overlying the charge detection region with means for connecting an alternating current to the electrodes and means for measuring the power dissipation of the alternating current.

Claim 36

A multichannel shift register comprising a body of semiconductor material of a uniform conductivity type, a thin insulating layer covering at least a portion of one surface of said body, a plurality of series of metal electrodes formed on the insulating layer, each series constituting one channel of the shift register and defining a path along the subjacent surface of the semiconductor body, the path having a single conductivity type, means for establishing charge carriers in the body of the semiconductor beneath a first electrode of each series, electrical circuit means interconnecting the electrodes to sequentially vary the bias on each series of electrodes and propagate a potential well stepwise along said path below the electrodes thereby translating the charge carriers through the semiconductor along said path, and detector means in each series associated with an electrode removed in the series from said first electrode for detecting the presence or absence of charge carriers in the semiconductor below its associated electrode.

Claim 37

A multichannel shift register comprising a body of semiconductor material of a uniform conductivity type, a thin insulating layer covering at least a portion of one surface of said body, a plurality of series of metal electrodes formed on the insulating layer, each series constituting one channel of the shift register and defining a path along the subjacent surface of the semiconductor body, the path having a single conductivity type, means for establishing charge carriers in the body of the semiconductor beneath a first electrode of each series, electrical circuit means interconnecting the electrodes to sequentially vary the bias on each series of electrodes and propagate a potential well stepwise along said path below the electrodes thereby translating the charge carriers through the semiconductor along said path, and detector means in each series associated with an electrode removed in the series from said first electrode for detecting the presence or absence of charge carriers in the semiconductor below its associated electrode.

Claim 38

A multichannel shift register comprising a semiconductor body, a thin insulating layer covering at least a portion of one surface of said body, an array of metal electrodes formed on the insulating layer, a plurality of input electrodes arranged along one side of the array, a plurality of output electrodes arranged along the opposite side of the array and a series of groups of transfer electrodes extending between each input electrode and an output electrode, each series comprising with its associated input and output electrodes one channel of the shift register, the spacing between electrodes in each series being less than the spacing between electrodes in adjacent series, each group of electrodes comprising a first electrode, a second electrode, and a third electrode in sequence, first, second and third conductors, respectively connected to every first, second and third electrodes, and electrical circuit means interconnected to vary sequentially the bias on the first, second and third conductors with electrical pulses which overlap, the shift register characterized in that the regions of the semiconductor body directly beneath each transfer electrode are of a single conductivity type.

Claim 39

A multichannel shift register comprising a semiconductor body, a thin insulating layer covering at least a portion of one surface of said body, an array of metal electrodes formed on the insulating layer, a plurality of input electrodes arranged along one side of the array, a plurality of output electrodes arranged along the opposite side of the array and a series of groups of transfer electrodes extending between each input electrode and an output electrode, each series comprising with its associated input and output electrodes one channel of the shift register, the spacing between electrodes in each series being less than the spacing between electrodes in adjacent series, each group of electrodes comprising a first electrode, a second electrode, and a third electrode in sequence, first, second and third conductors, respectively connected to every first, second and third electrodes, and electrical circuit means interconnected to vary sequentially the bias on the first, second and third conductors with electrical pulses which overlap, the shift register characterized in that the regions of the semiconductor body directly beneath each transfer electrode are of a single conductivity type.