Power source voltage tracking circuit for stabilization of bit lines

Claim 2

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage, said load means is a diode-connected MOS FET transistor coupled between said first node and output line; means coupled between said first and second nodes for charging said second node with a second voltage, said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor; and means for discharging said output line in response to said second voltage on said second node.

Claim 3

A circuit according to claim 1, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 4

A circuit according to claim 2, further comprising a fourth MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 5

A circuit according to claim 2, further comprising means for passing noise coupled between said second node, the reference potential and the power source voltage for passing the noise furnished to said second node.

Claim 6

A circuit according to claim 1, further comprising means for passing noise coupled between said second node, the reference potential and the power source voltage for passing the noise furnished to said second node.

Claim 7

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage; and means for discharging said output line in response to said second voltage on said second node, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 8

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage; and means for discharging said output line in response to said second voltage on said second node, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 9

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor; and means for discharging said output line in response to said second voltage on said second node.

Claim 10

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor; and means for discharging said output line in response to said second voltage on said second node.

Claim 11

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage; means for discharging said output line in response to said second voltage on said second node; and a MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 12

A power source voltage tracking circuit, comprising: a first node for receiving a power source voltage; a second node; an output line; load means coupled between said first node and output line to charge said output line with a first voltage lower in value than the power source voltage; means coupled between said first and second nodes for charging said second node with a second voltage; means for discharging said output line in response to said second voltage on said second node; and a MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 13

A power source voltage tracking circuit, comprising: an output line; load means coupled between a power source exhibiting an amplitude and said output line for charging said output line; means, for charging a second node, coupled between the power source and said second node, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor; and means exhibiting a threshold voltage, coupled between said output line, second node, power source and a reference potential for discharging said output line of its charged voltage when said amplitude of said power source drops below said threshold value.

Claim 14

A power source voltage tracking circuit, comprising: an output line; load means coupled between a power source exhibiting an amplitude and said output line for charging said output line; means, for charging a second node, coupled between the power source and said second node, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor; and means exhibiting a threshold voltage, coupled between said output line, second node, power source and a reference potential for discharging said output line of its charged voltage when said amplitude of said power source drops below said threshold value.

Claim 15

A circuit according to claim 9, wherein said load means is a diode-connected MOS FET transistor coupled between said power source and output line.

Claim 16

A circuit according to claim 10, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor.

Claim 17

A circuit according to claim 11, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 18

A circuit according to claim 12, further comprising a fourth MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 19

A circuit according to claim 13, further comprising means for passing noise coupled between said second node, the reference potential and the power source voltage for passing the noise furnished to said second node.

Claim 20

A circuit according to claim 9, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 21

A circuit according to claim 9, further comprising a MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 22

A circuit according to claim 9, further comprising means for passing noise coupled between said second node, the reference potential and the power source voltage for passing the noise furnished to said second node.

Claim 23

A random access memory device, comprising: a plurality of bit line pairs coupled with a plurality of memory cells; means for equalizing said bit line pairs connected between each pair of bit lines and a precharge line; load means coupled between a power source voltage and said precharge line for precharging said precharge line and said bit line pairs with a first voltage lower by a given voltage than the power source voltage; and means connected to an input terminal of said load means and an output terminal of said load means, for providing said precharge line and said bit line pairs with the first voltage, wherein said providing means further comprises: means coupled between said precharge line, a reference potential, a second node and the power source voltage, for discharging an output line; means coupled between the power source voltage and said second node, for charging said second node; and means coupled between said second node, the reference potential and the power source voltage, for passing noise furnished to said second node, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor.

Claim 24

A random access memory device, comprising: a plurality of bit line pairs coupled with a plurality of memory cells; means for equalizing said bit line pairs connected between each pair of bit lines and a precharge line; load means coupled between a power source voltage and said precharge line for precharging said precharge line and said bit line pairs with a first voltage lower by a given voltage than the power source voltage; and means connected to an input terminal of said load means and an output terminal of said load means, for providing said precharge line and said bit line pairs with the first voltage, wherein said providing means further comprises: means coupled between said precharge line, a reference potential, a second node and the power source voltage, for discharging an output line; means coupled between the power source voltage and said second node, for charging said second node; and means coupled between said second node, the reference potential and the power source voltage, for passing noise furnished to said second node, wherein said charging means is coupled in the form of a parallel connection between a plurality of series coupled diode-connected MOS FET transistors and a capacitor.

Claim 25

A device according to claim 18, wherein said load means is a diode-connected MOS FET transistor and said given voltage is a threshold voltage of said diode-connected MOS FET transistor.

Claim 26

A device as claimed in claim 18, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node.

Claim 27

A device as claimed in claim 18, said noise passing means comprises a MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.

Claim 28

A random access memory device, comprising: a plurality of bit line pairs coupled with a plurality of memory cells; means for equalizing said bit line pairs connected between each pair of bit lines and a precharge line; load means coupled between a power source voltage and said precharge line for precharging said precharge line and said bit line pairs with a first voltage lower by a given voltage than the power source voltage; and means connected to an input terminal of said load means and an output terminal of said load means, for providing said precharge line and said bit line pairs with the first voltage, wherein said providing means further comprises: means coupled between said precharge line, a reference potential, a second node and the power source voltage, for discharging an output line, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node; means coupled between the power source voltage and said second node, for charging said second node; and means coupled between said second node, the reference potential and the power source voltage, for passing noise furnished to said second node.

Claim 29

A random access memory device, comprising: a plurality of bit line pairs coupled with a plurality of memory cells; means for equalizing said bit line pairs connected between each pair of bit lines and a precharge line; load means coupled between a power source voltage and said precharge line for precharging said precharge line and said bit line pairs with a first voltage lower by a given voltage than the power source voltage; and means connected to an input terminal of said load means and an output terminal of said load means, for providing said precharge line and said bit line pairs with the first voltage, wherein said providing means further comprises: means coupled between said precharge line, a reference potential, a second node and the power source voltage, for discharging an output line, wherein said discharging means comprises: a first MOS FET transistor having a source-drain channel connected between said output line and a connection node, and a gate connected to said second node; a second MOS FET transistor having a drain-source channel connected between said connection node and a reference potential, and a gate connected to the power source voltage; and a third MOS FET transistor having a drain-source channel connected between said output line and the reference potential, and a gate connected to said connection node; means coupled between the power source voltage and said second node, for charging said second node; and means coupled between said second node, the reference potential and the power source voltage, for passing noise furnished to said second node.

Claim 30

A device as claimed in claim 22, said noise passing means comprises a fourth MOS FET having a drain-source channel connected between said second node and the reference potential, and a gate connected to the power source voltage.