Power supply noise protection circuit

Claim 2

A semiconductor integrated circuit having an input circuit, an internal circuit, and an output circuit formed together on a single chip, each of said circuits being connected to common power source lines, said input circuit comprising: a load circuit coupled between a power source potential supply terminal and a signal output terminal; first and second FETs, of the same conductivity type, serially connected between said signal output terminal and a common potential supply terminal and having a series connecting point therebetween, each of said first and second FETs having a gate connected to receive an input signal; a third FET connected between said power source potential supply terminal and the series connecting point of said first and second FETs, said third FET having a gate connected to said signal output terminal; a fourth FET, connected between a predetermined potential and the series connecting point of said first and second FETs, and control means, responsive to operation of either of said internal circuit or said output circuit, for turning on said fourth FET for a predetermined period of time when the operation of said terminal circuit or said output circuit is likely to cause the potentials of the common power source lines to fluctuate.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said output circuit has output buffer amplifiers and said control means turns on said fourth FET for a predetermined period of time the output buffers of said output circuit are driven.

Claim 4

A semiconductor integrated circuit according to claim 1, wherein said fourth FET is connected to said power source potential supply terminal.

Claim 5

A semiconductor integrated circuit according to claim 1, wherein said fourth FET is connected to said common potential supply terminal.

Claim 6

A semiconductor integrated circuit according to claim 3, wherein said semiconductor integrated circuit is a semiconductor memory and the input signal which is input to said input circuit is a row address strobe signal.

Claim 7

A semiconductor integrated circuit according to claim 3, wherein said semiconductor integrated circuit is a semiconductor memory and the input signal which is input to said input circuit is a column address strobe signal.

Claim 8

A semiconductor integrated circuit according to claim 3, wherein said semiconductor integrated circuit is a semiconductor memory and the input signal which is input to said input circuit is an output enable signal.

Claim 9

A semiconductor integrated circuit according to claim 4, wherein said semiconductor integrated circuit is a semiconductor memory and the input signal which is input to said input circuit is a write enable signal.

Claim 10

A semiconductor integrated circuit having an input circuit, an internal circuit, and an output circuit formed together on a single chip, each of said circuits being connected to common power source lines, said input circuit comprising: a load circuit coupled between a power source potential supply terminal and a signal output terminal; first and second FETSs, of the same conductivity type, serially connected between said signal output terminal and a common potential supply terminal and having a series connecting point therebetween, each of said first and second FETs having a gate connected to receive an input signal; a third FET connected between said power source potential supply terminal and the series connecting point of said first and second FETs, said third FET having a gate connected to said signal output terminal; a fourth and fifth FET connected between a predetermined potential and the series connecting point of said first and second FETs, said fifth FET having a gate connected to said signal output terminal; and control means, responsive to operation of either of said internal circuit or said output circuit, for turning on said fourth FET for a predetermined period of time when the operation of said internal circuit or said output circuit is likely to cause the potentials of the common power source lines to fluctuate.

Claim 11

A semiconductor integrated circuit having an input circuit, an internal circuit, and an output circuit formed together on a single chip, each of said circuits being connected to common power source lines, said input circuit comprising: a load circuit coupled between a power source potential supply terminal and a signal output terminal; first and second FETSs, of the same conductivity type, serially connected between said signal output terminal and a common potential supply terminal and having a series connecting point therebetween, each of said first and second FETs having a gate connected to receive an input signal; a third FET connected between said power source potential supply terminal and the series connecting point of said first and second FETs, said third FET having a gate connected to said signal output terminal; a fourth and fifth FET connected between a predetermined potential and the series connecting point of said first and second FETs, said fifth FET having a gate connected to said signal output terminal; and control means, responsive to operation of either of said internal circuit or said output circuit, for turning on said fourth FET for a predetermined period of time when the operation of said internal circuit or said output circuit is likely to cause the potentials of the common power source lines to fluctuate.

Claim 12

A semiconductor integrated circuit comprising: first and second FETs, of the same conductivity type, serially connected between a signal output terminal and a first common potential supply terminal and having a series connecting point therebetween, each of said first and second FETs having a gate connected to receive an input signal; means for coupling a second power source potential supply terminal to said signal output terminal; a third FET connected between one of said power source potential supply terminal and the series connecting point of said first and second FETs, said third FET having a gate connected to said signal output terminal, thereby forming with said first and second FETs a Schmitt trigger circuit having a hysteresis characteristic; and means for altering the hysteresis characteristic of said Schmitt trigger circuit comprising means for generating a control signal and a fourth FET connected between a predetermined potential and the series connecting point of said first and second FETs, said fourth FET turning on for a predetermined period of time in response to said control signal to alter said hysteresis characteristic.

Claim 13

A semiconductor integrated circuit comprising: first and second FETs, of the same conductivity type, serially connected between a signal output terminal and a first common potential supply terminal and having a series connecting point therebetween, each of said first and second FETs having a gate connected to receive an input signal; means for coupling a second power source potential supply terminal to said signal output terminal; a third FET connected between one of said power source potential supply terminal and the series connecting point of said first and second FETs, said third FET having a gate connected to said signal output terminal, thereby forming with said first and second FETs a Schmitt trigger circuit having a hysteresis characteristic; and means for altering the hysteresis characteristic of said Schmitt trigger circuit comprising means for generating a control signal and a fourth FET connected between a predetermined potential and the series connecting point of said first and second FETs, said fourth FET turning on for a predetermined period of time in response to said control signal to alter said hysteresis characteristic.