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US5284783A
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Method of fabricating a heterojunction bipolar transistor
Assignee: Fujitsu Ltd
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Filing: 1991-07-02
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Granted: 1994-02-08
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Expires: 2011-07-02
Abstract
Abstract A method of fabricating a semiconductor device having an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, the semiconductor material being doped to the p-type by addition of beryllium and selected from a group including gallium aluminum arsenide and indium gallium aluminum arsenide, in which the method comprises steps of growing the epitaxial layer on the underlying crystal layer, adding beryllium to a concentration level of about 5*1019 atoms/cm3 to about 5*1020 atoms/cm3 to the semiconductor material, and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in the semiconductor material.
Inventors
- 👤 Hideaki Ishikawa
- 👤 Toshio Fujii
- 👤 Eizo Miyauchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:11
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10P; H10P32/00; H10D62/00; H10D62/80; H10D62/85; H10D62/852; Y; Y10; Y10S; Y10S438/00; Y10S438/936
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
118 words
A method of fabricating a semiconductor device comprising an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, said semiconductor material being doped to the p-type by addition of beryllium and selected from a group consisting of gallium aluminum arsenide and indium gallium aluminum arsenide, said method comprising the steps of: growing said epitaxial layer on the underlying crystal layer; adding beryllium to a concentration level of about 5×10 19 atoms/cm 3 to about 5×10 20 atoms/cm 3 to the semiconductor material; and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in said semiconductor material.
Claim 2
Independent Claim
118 words
A method of fabricating a semiconductor device comprising an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, said semiconductor material being doped to the p-type by addition of beryllium and selected from a group consisting of gallium aluminum arsenide and indium gallium aluminum arsenide, said method comprising the steps of: growing said epitaxial layer on the underlying crystal layer; adding beryllium to a concentration level of about 5×10 19 atoms/cm 3 to about 5×10 20 atoms/cm 3 to the semiconductor material; and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in said semiconductor material.
Claim 3
Dependent Claim
31 words
A method as claimed in claim 1 in which said step of adding beryllium and said step of adding indium are carried out during said step of growing the epitaxial layer.
Claim 4
Dependent Claim
24 words
A method as claimed in claim 2 in which said step of adding beryllium and said step of adding indium are carried out simultaneously.
Claim 5
Dependent Claim
36 words
A method as claimed in claim 1 in which said underlying crystal layer consists of gallium arsenide, and said step of growing the epitaxial layer is made at a temperature between 550° C. and 680° C.
Claim 6
Dependent Claim
26 words
A method as claimed in claim 4 in which said step of growing the epitaxial layer is made at a temperature equal to about 600° C.
Claim 7
Dependent Claim
37 words
A method as claimed in claim 1 in which said epitaxial layer consists of indium gallium aluminum arsenide, and said step of growing the epitaxial layer is made at a temperature between 420° C. and 520° C.
Claim 8
Dependent Claim
25 words
A method as claimed in claim 6 in which said step of growing the epitaxial layer is made at a temperature of about 460° C.
Claim 9
Independent Claim
125 words
A method of fabricating a bipolar transistor, comprising steps of: growing an n-type collector layer on an underlying crystal layer epitaxially; growing a base layer of a group III-V compound semiconductor material selected from a group of materials consisting of gallium aluminum arsenide and indium gallium aluminum arsenide on the n-type collector layer epitaxially; doping the base layer to the p-type by adding beryllium to the base layer with a concentration level of about 5×10 19 atoms/cm 3 to about 5×10 20 atoms/cm 3 ; adding indium to the base layer by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements contained in the base layer; and growing an n-type emitter layer on said base layer.
Claim 10
Independent Claim
125 words
A method of fabricating a bipolar transistor, comprising steps of: growing an n-type collector layer on an underlying crystal layer epitaxially; growing a base layer of a group III-V compound semiconductor material selected from a group of materials consisting of gallium aluminum arsenide and indium gallium aluminum arsenide on the n-type collector layer epitaxially; doping the base layer to the p-type by adding beryllium to the base layer with a concentration level of about 5×10 19 atoms/cm 3 to about 5×10 20 atoms/cm 3 ; adding indium to the base layer by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements contained in the base layer; and growing an n-type emitter layer on said base layer.
Claim 11
Dependent Claim
30 words
A method as claimed in claim 8 in which said step of doping and said step of adding indium are carried out during said step of growing the base layer.
Claim 12
Dependent Claim
23 words
A method as claimed in claim 9 in which said step of doping and said step of adding indium are carried out simultaneously.
Claim 13
Dependent Claim
39 words
A method as claimed in claim 8 in which said base layer comprises gallium aluminum arsenide, and said growth of the base layer is made at a temperature in a range of about 550° C. to about 680° C.
Claim 14
Dependent Claim
24 words
A method as claimed in claim 11 in which said growth of the base layer is made at a temperature of about 600° C.
Claim 15
Dependent Claim
40 words
A method as claimed in claim 8 in which said base layer comprises indium gallium aluminum arsenide, and said growth of the base layer is made at a temperature in a range of about 420° C. to about 520° C.
Claim 16
Dependent Claim
67 words
A method as claimed in claim 8 in which said step of growing the base layer further comprises a step of providing a gradation of aluminum content in the base layer such that the aluminum content is increased continuously from a first side of the base layer in contact with the collector layer to a second side of the base layer in contact with the emitter layer.
Claim 17
Dependent Claim
68 words
A method as claimed in claim 8 in which said step of growing the emitter layer further comprises a step of providing a compositional gradation of aluminum content in the emitter layer such that the aluminum content increases continuously, remains constant, and then decreases continuously from a first side of the emitter layer in contact with the base layer to a second side opposite from said first side.
Claim 18
Independent Claim
85 words
A method of fabricating a semiconductor device comprising an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, said semiconductor material being doped to the p-type by addition of beryllium and selected from a group comprising gallium aluminum arsenide and indium gallium aluminum arsenide, comprising steps of: growing said epitaxial layer on the underlying crystal layer; adding beryllium to a predetermined concentration level; and adding indium by an amount generally equal to that of beryllium.
Claim 19
Independent Claim
85 words
A method of fabricating a semiconductor device comprising an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, said semiconductor material being doped to the p-type by addition of beryllium and selected from a group comprising gallium aluminum arsenide and indium gallium aluminum arsenide, comprising steps of: growing said epitaxial layer on the underlying crystal layer; adding beryllium to a predetermined concentration level; and adding indium by an amount generally equal to that of beryllium.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |