US5283457A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor on insulator transistor
Assignee: Texas Instruments Inc
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Filing: 1991-03-05
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Granted: 1994-02-01
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Expires: 2011-03-05
Abstract
Abstract The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor. In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor's channel.
Inventors
- 👤 Mishel Matloubian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:33
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
200 words
A transistor structure comprising: a semiconductor layer having a first conductivity type; a first drain region formed in said semiconductor layer, said first drain region having a second conductivity type; a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region; a second channel region having said second conductivity type formed in said semiconductive layer abutting said first channel region and disposed perpendicularly to said first channel region; a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.
Claim 2
Dependent Claim
200 words
A transistor structure comprising: a semiconductor layer having a first conductivity type; a first drain region formed in said semiconductor layer, said first drain region having a second conductivity type; a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region; a second channel region having said second conductivity type formed in said semiconductive layer abutting said first channel region and disposed perpendicularly to said first channel region; a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.
Claim 3
Dependent Claim
17 words
A transistor structure as in claim 1 wherein said semiconductive layer is formed on an insulating layer.
Claim 4
Dependent Claim
14 words
A transistor structure as in claim 2 wherein said insulating layer comprises silicon dioxide.
Claim 5
Dependent Claim
24 words
A transistor structure as in claim 1 wherein said gate is separated from said first and second channel regions by a gate dielectric layer.
Claim 6
Dependent Claim
15 words
A transistor structure as in claim 4 wherein said gate dielectric layer comprises silicon dioxide.
Claim 7
Dependent Claim
231 words
A transistor structure comprising: a semiconductive layer having a first conductivity type; a first drain region formed in said semiconductive layer, said first drain region having a second conductivity type; a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region; a second source region formed in said semiconductive layer, said second source region having said first conductivity type and said second source region abutting said first channel region; a second channel region having said second conductivity type formed in said semiconductive layer abutting said second source region, said second channel region disposed perpendicularly to said first channel region; a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.
Claim 8
Dependent Claim
231 words
A transistor structure comprising: a semiconductive layer having a first conductivity type; a first drain region formed in said semiconductive layer, said first drain region having a second conductivity type; a first source region formed in said semiconductive layer, said first source region having said second conductivity type, said first source region being separated from said first drain region by a first channel region; a second source region formed in said semiconductive layer, said second source region having said first conductivity type and said second source region abutting said first channel region; a second channel region having said second conductivity type formed in said semiconductive layer abutting said second source region, said second channel region disposed perpendicularly to said first channel region; a second drain region formed in said semiconductive layer, said second drain region having said first conductivity type, said second drain region being separated from said first channel region by said second channel region; and a T-shaped gate formed on the surface of said semiconductive layer over said first and second channel regions such that a first potential applied to said gate causes said first channel region to be conductive and said second channel region to be non conductive and such that a second potential applied to said gate causes said second channel region to be substantially conductive and to couple said first channel region to a reference potential.
Claim 9
Dependent Claim
17 words
A transistor structure as in claim 6 wherein said semiconductive layer is formed on an insulating layer.
Claim 10
Dependent Claim
14 words
A transistor structure as in claim 7 wherein said insulating layer comprises silicon dioxide.
Claim 11
Dependent Claim
24 words
A transistor structure as in claim 6 wherein said gate is separated from said first and second channel regions by a gate dielectric layer.
Claim 12
Dependent Claim
15 words
A transistor structure as in claim 9 wherein said gate dielectric layer comprises silicon dioxide.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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