US4384300A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Negative resistance device
Assignee: Toshiba Corp
•
Filing: 1981-04-14
•
Granted: 1983-05-17
•
Expires: 2001-04-14
Abstract
Abstract A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.
Inventors
- 👤 Tetsuya Iizuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:24
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
327 words
A negative resistance device comprising: a semiconductor substrate of a first conductivity type; a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; and a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and the channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer; and said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulation layer and overlapping the second and third regions.
Claim 2
Dependent Claim
327 words
A negative resistance device comprising: a semiconductor substrate of a first conductivity type; a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; and a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and the channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer; and said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulation layer and overlapping the second and third regions.
Claim 3
Dependent Claim
37 words
A negative resistance device according to claim 1, wherein a sixth region of the first conductivity type and a seventh region of the second conductivity type are formed in the second region and the third region, respectively.
Claim 4
Dependent Claim
344 words
A semiconductor device comprising a negative resistance device and a load resistor connected to the negative resistance device, said negative resistance device comprising: a semiconductor substrate of a first conductivity type; a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; and a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer; and said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulating layer and overlapping the second and third regions.
Claim 5
Dependent Claim
344 words
A semiconductor device comprising a negative resistance device and a load resistor connected to the negative resistance device, said negative resistance device comprising: a semiconductor substrate of a first conductivity type; a first IGFET of a first channel type formed in the semiconductor substrate, the first IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; and a second IGFET of a second channel type formed in the semiconductor substrate, the second IGFET having a drain terminal, a source terminal, a gate terminal, a substrate terminal, a drain region, a source region and a channel region; both the source terminal and gate terminal of said first IGFET being connected to the source and gate terminals of said second IGFET, the drain terminal of said first IGFET being connected to the substrate terminal of said second IGFET, the drain terminal of said second IGFET being connected to the substrate terminal of said first IGFET, and the drain regions and channel regions of said first and second IGFETs being formed below a common gate electrode layer and overlapping the common gate electrode layer; and said first and second IGFETs comprising a first region of a second conductivity type formed in the semiconductor substrate, a second region of the second conductivity type formed in the semiconductor substrate and in contact with the boundary between the semiconductor substrate and the first region, a third region of the first conductivity type formed in the first region and in contact with said boundary, a fourth region of the second conductivity type formed in the semiconductor substrate and disposed in contact with the second region and separated from said boundary, a fifth region of the first conductivity type formed in the first region and disposed in contact with the third region and separated from said boundary, an insulation layer formed on the surface of the second and third regions, and a common gate electrode layer formed on the insulating layer and overlapping the second and third regions.
Claim 6
Dependent Claim
36 words
A semiconductor device according to claim 3, wherein a sixth region of the first conductivity type and a seventh region of the second conductivity type are formed in the second region and the third region, respectively.
Claim 7
Dependent Claim
28 words
A semiconductor device according to claim 3, or 4 further comprising an IGFET connected to the node where said negative resistance device and said load resistor are connected.
Claim 8
Dependent Claim
16 words
A semiconductor device according to claims 3, or 4, wherein said load resistor is an IGFET.
Claim 9
Dependent Claim
99 words
A semiconductor device according to claim 3, or 4 wherein said load resistor includes a third IGFET of a first channel type connected at the drain terminal to said negative resistance device, a fourth IGFET of a seond channel type connected at the drain terminal to ground, the source and gate terminals of said third IGFET are connected to those of said fourth IGFET, the drain terminal of said third IGFET is connected to the substrate terminal of said fourth IGFET, and the drain terminal of said fourth IGFET is connected to the substrate terminal of said third IGFET.
Claim 10
Dependent Claim
18 words
A semiconductor device according to claim 3, or 4, wherein said load resistor is a diode inversely biased.
References Cited (Backward Citations)
DE2439875A1
Cited
US4064525A
Cited
FR2253284A1
Cited
US3968479A
Cited
US4053798A
Cited
US4231055A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-16 | 1986-11-15 | 1987-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-16 | 1990-11-15 | 1991-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-16 | 1994-11-15 | 1995-05-17 | $7700.00 | Window Closed / Lapsed |