Negative resistance device

Claim 2

A negative resistance device comprising: a complementary pair of FETs, each of which operates in depletion mode and includes a first pair of regions defining a source and drain and a second gate region and which are connected in series with each other by a first region of one FET connected to a first region of the other FET and by a gate region of each FET connected to at least one first region of the other FET, and a pair of external terminals respectively connected to a first region of each of said FETs which is not connected to the other FET at least one of said FETs being an insulated gate type non-volatile memory device comprising, at the gate region, an insulation film which stores electric charge therein to memorize in non-volatile manner.

Claim 3

A negative resistance device as in claim 1, wherein both FETs are said insulated gate type non-volatile memory devices.

Claim 4

A negative resistance device as in claim 1, wherein said at least one of said FETs is the insulated gate type non-volatile memory device in which electric charge is brought into the insulation film.

Claim 5

A negative resistance device as in claim 1, wherein said at least one of said FETs is an insulated gate type non-volatile memory device which has metal film as gate electrode, a first insulation film disposed underneath said metal film, and a second insulation film of different kind from and disposed underneath said first insulation film.

Claim 6

A negative resistance device as in claim 4 wherein said first insulation film is of Si 3 N 4 and said second insulation film is of SiO 2 .

Claim 7

A negative resistance device as in claim 1, wherein said complementary pair of FETs are made in a single semiconductor wafer.

Claim 8

A negative resistance device as in claim 1, wherein said at least one of said FETs of insulated gate type non-volatile memory device comprises a source electrode, a drain electrode, a gate electrode and a substrate electrode, said substrate electrode being connected to the connection point where both FETs are connected to each other.

Claim 9

A negative resistance device as in claim 1, which further comprises a diode inserted in series with one of said first regions.

Claim 10

A negative resistance device as in claim 8, wherein both FETs are said insulated gate type non-volatile memory devices.

Claim 11

A negative resistance device as in claim 8, wherein said at least one of said FETs is the insulated gate type non-volatile memory device in which electric charge is brought into the insulation film.

Claim 12

A negative resistance device as in claim 8, wherein said at least one of said FETs is an insulated gate type non-volatile memory device which has metal film as gate electrode, a first insulation film disposed underneath said metal film, and a second insulation film of different kind from and disposed underneath said first insulation film.

Claim 13

A negative resistance device as in claim 11, wherein said first insulation film is of Si 3 N 4 and said second insulation film is of SiO 2 .

Claim 14

A negative resistance device as in claim 8, wherein said complementary pair of FETs are made in a single semiconductor wafer.

Claim 15

A negative resistance device as in claim 8, wherein said at least one of said FETs of insulated gate type non-volatile memory device comprises a source electrode, a drain electrode, a gate electrode and a substrate electrode, said substrate electrode being connected to the connection point where both FETs are connected to each other.

Claim 16

A negative resistance device as in claim 8, wherein one of said FETs is formed in one part of semiconductor substrate, and the second other FET is formed in a well having opposite type conductivity to the semiconductor substrate, and said diode is formed in a part of a first region of the first FET.

Claim 17

A negative resistance device as in claim 1, wherein a diode is inserted between said first regions of said FETs which are series connected.

Claim 18

A negative resistance memory matrix comprising a plurality of devices connected between horizontal and vertical lines, each device comprising: a complementary pair of FETs, each of which operates in depletion mode and includes a first pair of regions defining a source and drain and a second gate region and which are connected in series with each other by a first region of one FET connected to a first region of the other FET and by a gate region of each FET connected to at least one first region of the other FET, and a pair of external terminals respectively connected to a first region of each of said FETs which is not connected to the other FET, at least one of said FETs being an insulated gate type non-volatile memory device comprising, at the gate region, an insulation film which stores electric charge therein to memorize in non-volatile manner, memorizing in each device being carried out by a D.C. writing voltage of a specified polarity and amplitude exceeding a threshold value, erasing by a D.C. voltage of opposite polarity to that of said writing voltage and amplitude exceeding said threshold value and reaching by other voltages of the same polarity as said writing voltage and amplitude such that a current is obtained in the Λ letter voltage-current characteristic of the device.

Claim 19

A negative resistance memory matrix comprising a plurality of devices connected between horizontal and vertical lines, each device comprising: a complementary pair of FETs, each of which operates in depletion mode and includes a first pair of regions defining a source and drain and a second gate region and which are connected in series with each other by a first region of one FET connected to a first region of the other FET and by a gate region of each FET connected to at least one first region of the other FET, and a pair of external terminals respectively connected to a first region of each of said FETs which is not connected to the other FET, at least one of said FETs being an insulated gate type non-volatile memory device comprising, at the gate region, an insulation film which stores electric charge therein to memorize in non-volatile manner, memorizing in each device being carried out by a D.C. writing voltage of a specified polarity and amplitude exceeding a threshold value, erasing by a D.C. voltage of opposite polarity to that of said writing voltage and amplitude exceeding said threshold value and reaching by other voltages of the same polarity as said writing voltage and amplitude such that a current is obtained in the Λ letter voltage-current characteristic of the device.

Claim 20

A negative resistance device as in claim 17, wherein said at least one of said FETs of insulated gate type non-volatile memory device comprises a source electrode, a drain electrode, a gate electrode and a substrate electrode, said substrate electrode being connected to the connection point where both FETs are connected to each other.

Claim 21

A negative resistance device as in claim 17, which further comprises a diode inserted in series with one of said first regions.