US3908182A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile memory cell
Assignee: Westinghouse Electric Corp
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Filing: 1974-05-08
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Granted: 1975-09-23
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Expires: 1994-05-08
Abstract
Abstract A memory cell combining CCD and MNOS technology comprised of a MNOS transistor having a reversible, electrically shiftable threshold wherein its memory-controlled gated source is connected in series with a MOSFET address switch transistor, with the address switch transistor and MNOS memory transistor being coupled in parallel with a CCD shift register stage by means of respective P+ diffused regions within separate wells of the CCD shift register. Preferably, each CCD shift register stage includes two receiving potential wells capable of holding minority carriers defined by two regions acting as barriers to the flow of minority carriers and having a multi-phase drive system operating the shift register. The non-volatile memory thus configured provides non-volatile storage outside the CCD shift register, in which the CCD signal charge controls the (memory write) address switch; and memory read-out is accomplished by parallel data charge injection via the memory-controlled gated source, with no logic inversion.
Inventors
- 👤 Donald R Lampe
- 👤 Marvin H White
- 👤 Franklyn C Blaha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:11
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C14/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H; H10; H10D; H10D84/00; H10D84/891
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
158 words
A FUNCTIONAL NON-VOLATILE MEMORY CELL COMPRISING IS COMBINATION: A STAGE OF CHARGE COUPLED DEVICE SHIFT REGISTER HAVING AT LEAST TWO POTENTIAL WELLS CAPABLE OF HOLDING MINORITY CARRIERS, AND A RESPECTIVE ADJACENT BARRIER TO THE FLOW OF MINORITY CARRIERS AND HAVING MEANS FOR APPLYING BIAS POTENTIALS TO SAID WELLS FOR SELECTIVELY MOVING AND HOLDING SAID MINORITY CARRIERS, FIRST AND SECOND MEANS RESPECTIVELY COUPLED TO SAID AT LEAST TWO WELLS, SAID MEANS BEING ADAPTED TO SELECTIVELY SENSE THE SURFACE POTENTIAL IN THE RESPECTIVE WELLS AS WELL AS INJECT CHARGE THEREIN, A SEMICONDUCTOR ADDRESS SWITCH DEVICE EXTERNAL TO SAID CHARGE COUPLED DEVICE SHIFT REGISTER AND HAVING A CONTROL ELECTRODE AND TWO CHARGE TRANSFER ELECTRODES, A SEMICONDUCTOR MEMORY DEVICE EXTERNAL TO SAID CHARGE COUPLED DEVICE SHIFT REGISTER AND HAVING A REVERSIBLE ELECTRICALLY-SHIFTABLE CONDUCTION THRESHOLD, A CONTROL ELECTRODE AND TWO CHARGE TRANSFER ELECTRODES, AND BEING CONNECTED IN SERIES WITH SAID SWITCH DEVICE BY MEANS OF A RESPECTIVE CHARGE TRANSFER ELECTRODE, WITH BOTH DEVICES
Claim 2
Dependent Claim
158 words
A FUNCTIONAL NON-VOLATILE MEMORY CELL COMPRISING IS COMBINATION: A STAGE OF CHARGE COUPLED DEVICE SHIFT REGISTER HAVING AT LEAST TWO POTENTIAL WELLS CAPABLE OF HOLDING MINORITY CARRIERS, AND A RESPECTIVE ADJACENT BARRIER TO THE FLOW OF MINORITY CARRIERS AND HAVING MEANS FOR APPLYING BIAS POTENTIALS TO SAID WELLS FOR SELECTIVELY MOVING AND HOLDING SAID MINORITY CARRIERS, FIRST AND SECOND MEANS RESPECTIVELY COUPLED TO SAID AT LEAST TWO WELLS, SAID MEANS BEING ADAPTED TO SELECTIVELY SENSE THE SURFACE POTENTIAL IN THE RESPECTIVE WELLS AS WELL AS INJECT CHARGE THEREIN, A SEMICONDUCTOR ADDRESS SWITCH DEVICE EXTERNAL TO SAID CHARGE COUPLED DEVICE SHIFT REGISTER AND HAVING A CONTROL ELECTRODE AND TWO CHARGE TRANSFER ELECTRODES, A SEMICONDUCTOR MEMORY DEVICE EXTERNAL TO SAID CHARGE COUPLED DEVICE SHIFT REGISTER AND HAVING A REVERSIBLE ELECTRICALLY-SHIFTABLE CONDUCTION THRESHOLD, A CONTROL ELECTRODE AND TWO CHARGE TRANSFER ELECTRODES, AND BEING CONNECTED IN SERIES WITH SAID SWITCH DEVICE BY MEANS OF A RESPECTIVE CHARGE TRANSFER ELECTRODE, WITH BOTH DEVICES
Claim 3
Dependent Claim
65 words
The memory cells as defined by claim 1 wherein said semiconductor address switch device comprises a field effect transistor switch and said semiconductor memory device comprises a metal-nitride-oxide-semiconductor transistor, each having a gate, a drain and a source, and wherein the series connection between the two transistors consists in the direct connection of the source of one transistor to the drain of the other transistor.
Claim 4
Dependent Claim
19 words
The memory cell as defined by claim 2 wherein said field effect transistor comprises a metal-oxide-semiconductor field effect transistor.
Claim 5
Dependent Claim
33 words
The memory cell as defined by claim 1 wherein said first and second means eaCh comprises a diffused semiconductor sense region proximate to the respective well in said charge coupled device shift register.
Claim 6
Dependent Claim
45 words
The memory cell as defined by claim 1 wherein said charge coupled device shift register stage includes four potential wells adapted to have separate synchronized clock bias potentials applied for providing two alternately located receiving wells and two barriers to the flow of minority carriers.
Claim 7
Dependent Claim
33 words
The memory cell as defined by claim 5 wherein the alternately located receiving wells comprises the first and third wells and the two wells acting as barriers comprises the second and fourth wells.
Claim 8
Dependent Claim
28 words
The memory cell as defined by claim 6 wherein said first means is coupled to said first well and said second means is coupled to said third well.
Claim 9
Dependent Claim
73 words
The memory cell as defined by claim 7 wherein said semiconductor address switch device comprises a field effect transistor and said semiconductor memory device comprises a metal-nitride-oxide-semiconductor transistor, each having a gate, a drain and a source and wherein the series connection between the field effect transistor and the metal-nitride-oxide-semiconductor transistor consists in the direct connection of the source of the metal-nitride-oxide-semiconductor memory transistor to the drain of the field effect switch transistor.
Claim 10
Dependent Claim
19 words
The memory cell as defined by claim 8 wherein said field effect transistor comprises a metal-oxide-semiconductor field effect transistor.
Claim 11
Dependent Claim
80 words
The memory cell as defined by claim 9 wherein the gate of the field effect transistor is connected to said first means, said drain of the metal-nitride-oxide-semiconductor transistor is connected to said second means, the source of said field effect transistor is connected to a first bias potential line, and said gate of the metal-nitride-oxide-semiconductor transistor is connected to the second bias potential line, and wherein the substrate of said metal-nitride-oxide-semiconductor transistor is connected to a third bias potential line.
Claim 12
Dependent Claim
21 words
The memory cell as defined by claim 10 wherein said first and second means each comprises a surface potential sense region.
Claim 13
Dependent Claim
22 words
The memory cell as defined by claim 11 wherein said sense region comprises a diffused sense region located within the respective well.
References Cited (Backward Citations)
US3654499A
Cited
US3728695A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-22 | 1979-03-24 | 1979-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-22 | 1983-03-24 | 1983-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-22 | 1987-03-24 | 1987-09-23 | $7700.00 | Window Closed / Lapsed |