Complementary semiconductor memory device

Claim 1

A memory cell consisting essentially of two complementary metal-insulator-semiconductor (MIS) transistors integrated into a single semiconductor substrate with a single area portion of a single insulated gate serving entirely as the gates of said two MIS transistors, each said cell further consisting of: a semiconductor substrate having a first conductivity type, said substrate comprising the channel region of the first of said two MIS transistors, first and second spaced regions of conductivity type opposite to that of said substrate, said first and second spaced regions and the intervening portion of said substrate corresponding to the first of said two MIS transistors, a third region of the conductivity type of said substrate formed in said second region, said substrate and said second and third regions corresponding to the second of said two MIS transistors, a gate insulating layer and a gate electrode forming said single gate, and extending between said first and third regions, a field oxide layer extending into said substrate and having a configuration surrounding said third region except on the side of said third region on which said single gate is formed, said second and third regions both abutting at least in part horizontally with said first oxide along respective portions of the border of said field oxide around said cell, and no other portion of said field oxide being in contact with said third region, said single gate electrode with said single gate area portion extending in a single solid pattern on the gate insulating layer from said first region to said third region, said gate electrode having a configuration corresponding to self-alignment with respect to said first and second regions to extend at least to some extent over said first and third regions, said third region having a configuration corresponding to self-alignment with said respective portion of the border of said field oxide and said gate insulating layer, and said third size being of a minimum region for accommodating a single electrode contact thereto, necessary corresponding electrodes for activating each of said first and third regions and for grounding said substrate, said second region being floating electrically, for changing the threshold voltage of said second MIS transistor as a result of charges transferred by said first MIS transistor and stored in said second region.