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JPS6235559A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: National Institute of Advanced Industrial Science and Technology
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Filing: 1985-08-09
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Granted: —
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Expires: 2005-08-09
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Abstract

Abstract PURPOSE:To reduce the occupying area of an element by extending a substrate to form a terminal for the substrate, and controlling the number of majority carriers in the substrate. CONSTITUTION:A source 12 and a drain 13 are separately formed in the first silicon layer 11, the first gate electrode 15 is formed through a gate oxide film 14 on a channel region between the source 12 and the drain 13 and the N-channel first MOS transistor 10 is formed. The layer 1 is extended 1.5mum in a direction perpendicular to the source and drain direction, and a terminal 17 for the substrate is formed at the end. The second gate electrode 19 is formed through a gate oxide film 18 on the second silicon layer 16 to operate as the second MOS transistor 20. The gate electrode 15 and the drain 13 are connected with reading word line RW and bit line RB to operate as a memory circuit.

Inventors

  • 👤 Koichi Kato
  • 👤 弘一 加藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 08:44
CPC Classifications
H; H10; H10B; H10B12/00

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5357777A Cited
JPS5893370A Cited

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