Bus controller for adjusting a bus master to a bus slave

Claim 2

A bus controller used for a data processing system having a data processor as a bus master, the bus controller connected between the bus master and a bus slave via a bus to transfer data between the bus master and the bus slave with a plurality of different data port widths, wherein the improvement of said bus controller comprises: a port size correspondence table provided therein; determination means for obtaining port size information from master address information using said correspondence table in a bus cycle; a bus size determination circuit for obtaining port size information from address information from said data processor using an incorporated port size correspondence table which indicates the correspondence between address areas of said data processing system and port sizes; a bus timing circuit for receiving a reference clock, a master bus timing signal, a master byte control signal a slave transfer completion signal, and said port size signal and for outputting a slave bus timing signal, a master transfer completion signal, and a divided bus cycle number signal; an address bus interface circuit for receiving a master bus cycle type signal, a master address signal, a master byte control signal, and said divided bus cycle number signal and for outputting a slave bus cycle type signal, a slave address signal, and a slave byte control signal; and a data bus interface circuit for receiving a master bus cycle type signal, a master byte control signal, and said port size signal and divided bus cycle number signal and for determining a connection condition between said master data bus and said slave data bus for making connection.

Claim 3

The bus controller of claim 1, wherein said bus size determination circuit comprises: at least one address area determination circuit for receiving a predetermined significant bit of a master address signal to determine if each bit agrees with a value set in an address area designation register and makes an output significant when all bits agree; at least one port size designation circuit for outputting a value set in a port size designation register when said output is significant, a pair of said address area determination circuit and said port size designation circuit provided for each address area; and an OR gate for ORing respective outputs to output a port size signal.

Claim 4

A bus controller used for a data processing system having a data processor as a bus master, the bus controller connected between the bus master and a bus slave via a bus to transfer data between the bus master and the bus slave with a plurality of different data port widths, wherein the improvement of said bus controller comprises: a port size correspondence table provided therein, said port size correspondence table producing port width information responsive to address information for a plurality of different port widths; determination means, coupled to said port size correspondence table, for obtaining port size information from master address information using said correspondence table in a bus cycle; a bus size determination circuit for obtaining port size information from address information from said data processor using an incorporated port size correspondence table which indicates the correspondence between address areas of said data processing system and port sizes; a bus timing circuit for receiving a reference clock, a master bus timing signal, a master byte control signal, a slave transfer completion signal, and said port size signal and for outputting a slave bus timing signal, a master transfer completion signal, and a divided bus cycle number signal; an address bus interface circuit for receiving a master bus cycle type signal, a master address signal, a master byte control signal, and said divided bus cycle number signal and for outputting a slave bus cycle type signal, a slave address signal, and a slave byte control signal; and a data bus interface circuit for receiving a master bus cycle type signal, a master byte control signal, and said port size signal and divided bus cycle number signal and for determining a connection condition between said master data bus and said slave data bus for making connection.

Claim 5

A bus controller used for a data processing system having a data processor as a bus master, the bus controller connected between the bus master and a bus slave via a bus to transfer data between the bus master and the bus slave with a plurality of different data port widths, wherein the improvement of said bus controller comprises: a port size correspondence table provided therein, said port size correspondence table producing port width information responsive to address information for a plurality of different port widths; determination means, coupled to said port size correspondence table, for obtaining port size information from master address information using said correspondence table in a bus cycle; a bus size determination circuit for obtaining port size information from address information from said data processor using an incorporated port size correspondence table which indicates the correspondence between address areas of said data processing system and port sizes; a bus timing circuit for receiving a reference clock, a master bus timing signal, a master byte control signal, a slave transfer completion signal, and said port size signal and for outputting a slave bus timing signal, a master transfer completion signal, and a divided bus cycle number signal; an address bus interface circuit for receiving a master bus cycle type signal, a master address signal, a master byte control signal, and said divided bus cycle number signal and for outputting a slave bus cycle type signal, a slave address signal, and a slave byte control signal; and a data bus interface circuit for receiving a master bus cycle type signal, a master byte control signal, and said port size signal and divided bus cycle number signal and for determining a connection condition between said master data bus and said slave data bus for making connection.

Claim 6

The bus controller of claim 3, wherein said bus size determination circuit comprises: at least one address area determination circuit for receiving a predetermined significant bit of a master address signal to determine if each bit agrees with a value set in an address area designation register and makes an output significant when all bits agree; at least one port size designation circuit for outputting a value set in a port size designation register when said output is significant, a pair of said address area determination circuit and said port size designation circuit provided for each address area; and an OR gate for ORing respective outputs to output a port size signal.