US5088028A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Lock converting bus-to-bus interface system
Assignee: Techsearch LLC
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Filing: 1991-06-17
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Granted: 1992-02-11
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Expires: 2011-06-17
Abstract
Abstract A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.
Inventors
- 👤 John G. Theus
- 👤 Jeffrey L. Beachy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:13
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4031
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
439 words
An apparatus for providing data communications between first and second computer systems, each computer system having a bus master coupled to a bus to arbitrate for control of the bus, to read and write access data storage locations mapped to separate addresses within an address space, and then to relinquish control of the bus, with a bus master writing or reading data to or from a particular data storage location by placing on the bus an address to which the particular data storage location is mapped and transmitting or receiving the data via the bus, the apparatus comprising: first means coupled to the first computer system bus for mapping an address within the first computer system address space to an address within the second computer system address space as a function of first mapping data loaded into the first mapping means, for asserting a first request signal for access to an internal bus of the apparatus as a function of the address from the first computer system and the first mapping data, and for receiving a first lock signal from the first computer system, the first lock signal barring access to the first computer system bus by other devices of the first computer system; second means coupled to the second computer system bus for mapping an address within the second computer system address space to an address within the first computer system address space as a function of second mapping data loaded into the second mapping means, for asserting a second request signal for access to the internal bus of the apparatus as a function of the address from the second computer system and the second mapping data, and for receiving a second lock signal from the second computer system, the second lock signal barring access to the second computer system bus by other devices of the second computer system; and means coupled to the first and second mapping means for arbitrating for access to the internal bus in response to the first and second request signals, for controlling data flow between the first computer system and the second computer system via the internal bus of the apparatus when the internal bus is accessed by one of the computer systems according to the result of arbitrating between the first and second request signals, and for converting the first lock signal to the second lock signal, and vice versa, so that when the first computer system has access to the internal bus and asserts the first lock signal the bus of the second computer system is locked to bar access by devices of the second computer system, and vice versa.
Claim 2
Independent Claim
439 words
An apparatus for providing data communications between first and second computer systems, each computer system having a bus master coupled to a bus to arbitrate for control of the bus, to read and write access data storage locations mapped to separate addresses within an address space, and then to relinquish control of the bus, with a bus master writing or reading data to or from a particular data storage location by placing on the bus an address to which the particular data storage location is mapped and transmitting or receiving the data via the bus, the apparatus comprising: first means coupled to the first computer system bus for mapping an address within the first computer system address space to an address within the second computer system address space as a function of first mapping data loaded into the first mapping means, for asserting a first request signal for access to an internal bus of the apparatus as a function of the address from the first computer system and the first mapping data, and for receiving a first lock signal from the first computer system, the first lock signal barring access to the first computer system bus by other devices of the first computer system; second means coupled to the second computer system bus for mapping an address within the second computer system address space to an address within the first computer system address space as a function of second mapping data loaded into the second mapping means, for asserting a second request signal for access to the internal bus of the apparatus as a function of the address from the second computer system and the second mapping data, and for receiving a second lock signal from the second computer system, the second lock signal barring access to the second computer system bus by other devices of the second computer system; and means coupled to the first and second mapping means for arbitrating for access to the internal bus in response to the first and second request signals, for controlling data flow between the first computer system and the second computer system via the internal bus of the apparatus when the internal bus is accessed by one of the computer systems according to the result of arbitrating between the first and second request signals, and for converting the first lock signal to the second lock signal, and vice versa, so that when the first computer system has access to the internal bus and asserts the first lock signal the bus of the second computer system is locked to bar access by devices of the second computer system, and vice versa.
Claim 3
Dependent Claim
42 words
The apparatus according to claim 1 wherein the arbitrating, controlling and converting means comprises means for relinquishing control of the computer system bus being held by the converted lock signal when the asserted lock signal is removed by the other computer system.
Claim 4
Dependent Claim
38 words
The apparatus according to claim 1 wherein the arbitrating, controlling and converting means further comprises means for loading from one of the computer systems the first and second mapping data into the first and second mapping means, respectively.
Claim 5
Dependent Claim
196 words
The apparatus according to claim 1 wherein the arbitrating, controlling and converting means comprises: a first arbitration/control means for requesting access to the internal bus for the first computer system upon receipt of the first request signal, for controlling access between the internal bus and the first computer system in response to a first grant signal, and for converting the second lock signal to the first lock signal to hold the first computer system bus when the second lock signal is asserted and the second computer system initiates access to the internal bus; a second arbitration/control means for requesting access to the internal bus for the second computer system upon receipt of the second request signal, for controlling access between the internal bus and the second computer system in response to a second grant signal, and for converting the first lock signal to the second lock signal to hold the second computer system bus when the first lock signal is asserted and the first computer system initiates access to the internal bus; and a local arbitration circuit for generating the first and second grant signals in response to request from the first and second arbitration/control means.
References Cited (Backward Citations)
US4257095A
Cited
US4237534A
Cited
US4488217A
Cited
US4245307A
Cited
US4315310A
Cited
US4633392A
Cited
US4695944A
Cited
US4868741A
Cited
US4870704A
Cited
US4851990A
Cited
US4858234A
Cited
US4864496A
Cited
US4947366A
Cited
US4878166A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-10 | 1995-08-12 | 1996-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-10 | 1999-08-12 | 2000-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-10 | 2003-08-12 | 2004-02-11 | $7700.00 | Window Closed / Lapsed |