Circuits for accessing a variable width data bus with a variable width data field

Claim 1

In a data processing system including a variable width data bus for the parallel transmission of data in variable width fields or blocks between units in the data processing system, a logic circuit combination for placing a variable width data field having a number of bits from a first bit up to a last bit N f on a single variable width data bus comprising: means for aligning the first bit of a given one of said variable width data fields having a number of bits, N f , with a selected bit position n of a single data bus of width from a first bit position up to last bit position of number N c , where N f is any integer number of bits from 1 up to and including the number N c , where n is any bit position within the data bus width N c , and where N c is the last bit position, and means for determining whether the number of bits, N f , of said data field is greater than, equal to, or less than the number of bit positions between selected bit position n and last bit position N c , means responsive to said determining means for genreating select signals indicating which bit positions of said data bus contain valid data bits when the number of said bits, N f , of said data field placed in said data bus is less than the number of bit positions between n and N c , means responsive to said determining means for generating overflow signals indicating which bits of said data field remain beyond the bits placed in bit positions n to N c of said data bus when the number of bits, N f , of said data field is greater than the number of bit positions between n and N c , the amount of said data field bits in excess of the bits aligned between n and N c beyond these aligned up to N c being N f =(N c -m+1), and means responsive to said determining means and said overflow signals for placing said N f =(N c -n+1) bits of said data field beyond bit position N c of said data bus into the first bit position of said data bus up to the N f -(N c -n+1) bit position of said data bus.