Signal translator

Claim 2

In vertical processing apparatus having a memory, an arithmetic and logic section and control circuit means for transferring selected vertical slices of data from said memory for processing by said arithmetic and logic section in accordance with a program, and clock signal means for producing clock signals for timing the operation of said memory, said arithmetic and logic section, each vertical data slice including up to N data digits and the control circuit means being operable to provide up to N data signals at N corresponding data positions for each data transfer; the improvement comprising: data skewing means included in the control circuit means for skew transferring said data signals a number of said data positions in increments of Rx position, the sum of the increments being equal to said number, with each incremental data transfer occurring during a single clock cycle, where R is the radix and X has integer values.

Claim 3

The invention according to claim 1 wherein said data skewing means performs successive Rx position increments of data transfer in consecutive clock cycles.

Claim 4

The invention according to claim 2 wherein said data skewing means includes N networks each of which includes: a. an output lead associated with a corresponding data position, and b. Y data input leads adapted to receive the data signals from those data positions which are different Rx increments away from the associated data position; wherein said data skewing means further includes means for providing to each of said networks control signals each indicative of different Rx position increments and during consecutive clock cycles; and wherein each said network responds to said control signals during consecutive clock cycles to couple its output lead to that one of its Y input leads which corresponds to a current Rx valued control signal.

Claim 5

The invention according to claim 3 wherein said control signal providing means includes: a. means for providing a code indicative of said number of data positions of transfer; and b. means responsive to said code and to said clock signal means to provide the control signals.

Claim 6

The invention according to claim 4 wherein the radix R equals two; wherein said means responsive to the code includes a. a register for temporarily storing a binary number having Y orders, and indicative of said code, each order of which represents a different power of two transfer increment, said binary number being indicative of the total number of data positions to be skew transferred; b. Y control leads corresponding in order to the orders of said binary number; said Y control leads being coupled to each of said networks; c. means for detecting during successive clock cycles the most significant bit of one binary value in said register and for producing a control signal on the correspondingly ordered one of the Y leads to thereby effect an incremental power of two data transfer; and d. means responsive to the detection of said most significant bit during each clock cycle to change its value to the other binary value such that the incremental powers of two data transfers called for by said binary number are performed during consecutive clock cycles.

Claim 7

A data shifting network in which data is shifted in increments of powers of two, said network comprising circuit means having N data positions with each data position having a destination lead and a source lead, said circuit means further including means for producing N data signals on said N source leads; a clock signal generator for producing clock signals; N gating networks associated with corresponding ones of said data positions, each said network having Y gating paths coupled from the corresponding source lead to Y destination leads which are different powers of two data positions away; a register for temporarily storing a binary number having Y orders, each of which represents a different power of two shift increment, said binary number being indicative of the total number of data positions to be shifted; Y control leads corresponding in order to the orders of said binary number and being coupled to corresponding ones of the Y gating paths in said N-networks; detection means including means for detecting during successive clock cycles the most significant bit of one binary value in said register and producing a control signal on the correspondingly ordered one of said Y leads, which control signal enables the corresponding power of two gating path in each of said networks, thereby effecting an incremental data shift of a power of two data positions in one clock cycle; and means responsive to said detection of a most significant bit of one binary value during each clock cycle to change its value to the other binary value such that the incremental powers of two data shifts called for by said binary number are performed during consecutive clock cycles.

Claim 8

A data shifting network in which data is shifted in increments of powers of two, said network comprising circuit means having N data positions with each data position having a destination lead and a source lead, said circuit means further including means for producing N data signals on said N source leads; a clock signal generator for producing clock signals; N gating networks associated with corresponding ones of said data positions, each said network having Y gating paths coupled from the corresponding source lead to Y destination leads which are different powers of two data positions away; a register for temporarily storing a binary number having Y orders, each of which represents a different power of two shift increment, said binary number being indicative of the total number of data positions to be shifted; Y control leads corresponding in order to the orders of said binary number and being coupled to corresponding ones of the Y gating paths in said N-networks; detection means including means for detecting during successive clock cycles the most significant bit of one binary value in said register and producing a control signal on the correspondingly ordered one of said Y leads, which control signal enables the corresponding power of two gating path in each of said networks, thereby effecting an incremental data shift of a power of two data positions in one clock cycle; and means responsive to said detection of a most significant bit of one binary value during each clock cycle to change its value to the other binary value such that the incremental powers of two data shifts called for by said binary number are performed during consecutive clock cycles.

Claim 9

The invention as set forth in claim 6 wherein said detection means also includes means for detecting when the orders of said binary number are all of the other binary value; and wherein means responsive to said detection of all the binary number orders being of the other value disables said detection means and said value changing means.