US3571803A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arithmetic unit for data processing systems
Assignee: AT&T Inc
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Filing: 1968-06-04
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Granted: 1971-03-23
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Expires: 1988-06-04
Abstract
Abstract An arithmetic unit of a data processing system having the capability of designating any digit position of the data words being processed as the most significant digit position to thereby increase the efficiency of processing. More than one most significant digit position in a data word may be so designated. Designating a most significant digit position is realized by circuitry in the arithmetic unit which (1) inhibits data from being shifted from the most significant digit position to adjacent positions in one direction, (2) inhibits arithmetic carrys from propagating from the most significant digit position to said adjacent positions, and (3) causes the sign digit of a data word to be copied into the most significant digit position as well as being shifted to adjacent positions in the other direction on certain ''''arithmetic'''' shifts of the data word.
Inventors
- 👤 John H Huttenhoff
- 👤 Richard R Shively
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:39
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3812; G06F2207/3816
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
147 words
In a data processing system having a central control unit, at least one multidigit position register for registering data words, and shift logic responsive to said control unit for shifting the data words in said register; means for applying data signals to any digit position of said register to designate said position as the most significant digit position for arithmetic operations; means responsive to said signals for inhibiting the shifting of data from said designated position to a position adjacent thereto in one direction and for inhibiting the shifting of data from said adjacent position into said designated position; and means responsive to said signals for causing the data registered in said designated position to be reregistered therein as well as shifted to a position adjacent thereto in a second direction when said shift logic causes the shifting of data in said second direction in said register.
Claim 2
Dependent Claim
147 words
In a data processing system having a central control unit, at least one multidigit position register for registering data words, and shift logic responsive to said control unit for shifting the data words in said register; means for applying data signals to any digit position of said register to designate said position as the most significant digit position for arithmetic operations; means responsive to said signals for inhibiting the shifting of data from said designated position to a position adjacent thereto in one direction and for inhibiting the shifting of data from said adjacent position into said designated position; and means responsive to said signals for causing the data registered in said designated position to be reregistered therein as well as shifted to a position adjacent thereto in a second direction when said shift logic causes the shifting of data in said second direction in said register.
Claim 3
Dependent Claim
35 words
In a system as in claim 1 further comprising means for simultaneously applying signals to a plurality of the digit positions of said register to thereby designate said positions as the most significant digit positions.
Claim 4
Dependent Claim
160 words
A data processing system comprising a signal source; An arithmetic unit which includes; a plurality of identical cells each interconnected to two adjacent cells for registering and processing data; and means responsive to said signal source for shifting the data registered in each cell to adjacent cells; means for applying signal to any cell of said arithmetic unit to designate said cell as the most significant digit position for arithmetic operations; means responsive to said signals for inhibiting the shifting of data from said designated cell to an adjacent cell in a predetermined direction and for inhibiting the shifting of data into said designated cell from said adjacent cell; and means responsive to said signals for causing the data registered in said designated cell to be reregistered therein as well as shifted to the adjacent cell in the direction opposite said predetermined direction when said shifting means causes the shifting of data in said opposite direction in said identical cues.
Claim 5
Dependent Claim
160 words
A data processing system comprising a signal source; An arithmetic unit which includes; a plurality of identical cells each interconnected to two adjacent cells for registering and processing data; and means responsive to said signal source for shifting the data registered in each cell to adjacent cells; means for applying signal to any cell of said arithmetic unit to designate said cell as the most significant digit position for arithmetic operations; means responsive to said signals for inhibiting the shifting of data from said designated cell to an adjacent cell in a predetermined direction and for inhibiting the shifting of data into said designated cell from said adjacent cell; and means responsive to said signals for causing the data registered in said designated cell to be reregistered therein as well as shifted to the adjacent cell in the direction opposite said predetermined direction when said shifting means causes the shifting of data in said opposite direction in said identical cues.
Claim 6
Dependent Claim
135 words
An arithmetic unit of a data processing system comprising; a plurality of identical cells each interconnected to two adjacent cells, said identical cells including a plurality of data storage registers for storing data word digits and also including adder means for processing the data word digits of selected ones of said registers to obtain partial sums and arithmetic carrys; means for applying data words to and retrieving data words from said identical cells; means for shifting the partial sums and arithmetic carrys obtained in the identical cells to adjacent cells; and each of said identical cells further including circuitry responsive to applied signals for inhibiting the shifting of partial sums obtained in the cell to the adjacent cell in a fIrst direction whereby the cell is designated as the most significant position of said unit.
Claim 7
Dependent Claim
135 words
An arithmetic unit of a data processing system comprising; a plurality of identical cells each interconnected to two adjacent cells, said identical cells including a plurality of data storage registers for storing data word digits and also including adder means for processing the data word digits of selected ones of said registers to obtain partial sums and arithmetic carrys; means for applying data words to and retrieving data words from said identical cells; means for shifting the partial sums and arithmetic carrys obtained in the identical cells to adjacent cells; and each of said identical cells further including circuitry responsive to applied signals for inhibiting the shifting of partial sums obtained in the cell to the adjacent cell in a fIrst direction whereby the cell is designated as the most significant position of said unit.
Claim 8
Dependent Claim
36 words
An arithmetic unit as in claim 4 wherein said identical cells each further comprise means responsive to said applied signals for inhibiting the shifting of partial sums obtained in said adjacent cell to said designated cell.
Claim 9
Dependent Claim
35 words
An arithmetic unit as in claim 5 wherein said identical cells each further comprise means responsive to applied said signals for inhibiting the shifting of arithmetic carrys from said designated cell to said adjacent cell.
Claim 10
Dependent Claim
64 words
An arithmetic unit as in claim 6 wherein said identical cells each further comprise means responsive to said applied signals for causing any partial sums obtained in said designated cell to be reregistered therein and to be shifted to the adjacent cell in a second direction upon the shifting or partial sums in said second direction in said identical cells by said shifting means.
Claim 11
Dependent Claim
33 words
An arithmetic unit as in claim 7 further comprising means for simultaneously applying signals to a plurality of cells to designate said plurality cells as the most significant positions of said arithmetic unit.
Claim 12
Dependent Claim
157 words
In a data processing system having a signal source and an arithmetic unit, said arithmetic unit comprising a plurality of multidigit position registers for registering data, adder means for combining the registered data of the corresponding digit positions of selected ones of said registers to generate partial sums and arithmetic carrys, and circuitry responsive to said signal source for causing said partial sums and arithmetic carrys to be shifted and applied to digit positions of said registers adjacent to those positions in which said sums and carrys were generated; means for applying signals to any digit position of one of said registers and to the corresponding position of said adder means to designate said position as the most significant digit position for arithmetic operations; and means responsive to said signals for inhibiting the generation of said partial sums in said designated position when said circuitry causes shifting of partial sums in a predetermined direction in said registers.
Claim 13
Dependent Claim
157 words
In a data processing system having a signal source and an arithmetic unit, said arithmetic unit comprising a plurality of multidigit position registers for registering data, adder means for combining the registered data of the corresponding digit positions of selected ones of said registers to generate partial sums and arithmetic carrys, and circuitry responsive to said signal source for causing said partial sums and arithmetic carrys to be shifted and applied to digit positions of said registers adjacent to those positions in which said sums and carrys were generated; means for applying signals to any digit position of one of said registers and to the corresponding position of said adder means to designate said position as the most significant digit position for arithmetic operations; and means responsive to said signals for inhibiting the generation of said partial sums in said designated position when said circuitry causes shifting of partial sums in a predetermined direction in said registers.
Claim 14
Dependent Claim
44 words
In a system as in claim 9 further comprising means responsive to said signals for inhibiting the application of said partial sums to said designated position when said circuitry causes shifting of partial sums in the direction opposite said predetermined direction in said registers.
Claim 15
Dependent Claim
33 words
In a system as in claim 10 further comprising means responsive to said signals for inhibiting the application of said carrys to the position adjacent to said designated position in said predetermined direction.
Claim 16
Dependent Claim
50 words
In a system as in claim 11 further comprising means responsive to said signals and to a shift of data in said opposite direction in said registers for registering in said designated position and in the adjacent position in said opposite direction the partial sums generated in said designated position.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |