Abstract The invention relates to memory-mapping and protection facilities in multi-processor data-handling systems. A feature of the invention relates to systems in which a plurality of processors, including both arithmetic processors and processors for the control of external data handling devices, communicate with each other and with a main store using a shared data-bus. Addresses generated by the processors are split into a most significant part A and a least significant part B. The part A is used to address a table store which generates the most significant digits P of the main store address, with an indication Q of the type of access permitted (e.g. read only or read and write). The digits P and B serve to form the address of a main store location or a device control processor function, the digits Q being communicated with them over the data-bus and used to address in a controlled manner, main store locations and device control processor functions. In the preferred implementation the table store holds a large number (e.g. 64) of tables and a table number store holds, for each processor the number of the table currently in use. This enables processors to be allocated tables rapidly and independently the table allocated being set to suit the task to be undertaken.
A data processing system for expanding the address capability of individual microprocessors sharing a common store, which comprises: a plurality of processors each capable of internally generating a digital addressing word of A+B digits; a main store common to all of said processors and having a plurality of storage regions each containing a plurality of storage areas, each storage area being addressable by a digital addressing word of Z+B digits where Z is greater than A; a table store separate from said main store and common to all of said processors, said table store comprising a plurality of tables each providing a plurality of digital codewords of Z digits; a shared data-bus connecting all of said microprocessors, said main store and said table store; a control unit connected to said data-bus to control the data-bus for access by a selected processor to the table store and the main store and to address a particular table of said table store in accord with the selected processor, to pass the A digits of the addressing word of the selected processor to said particular table and thereby address a particular codeword of said particular table, and to pass the Z digits of said particular codeword, together with the B digits of said addressing word of the selected processor to address a particular storage area of said main store whereby to expand the address capability of the selected processor by the value 2.sup.(Z+B) -2.sup.(A+B).
Claim 2
Dependent Claim
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A data processing system for expanding the address capability of individual microprocessors sharing a common store, which comprises: a plurality of processors each capable of internally generating a digital addressing word of A+B digits; a main store common to all of said processors and having a plurality of storage regions each containing a plurality of storage areas, each storage area being addressable by a digital addressing word of Z+B digits where Z is greater than A; a table store separate from said main store and common to all of said processors, said table store comprising a plurality of tables each providing a plurality of digital codewords of Z digits; a shared data-bus connecting all of said microprocessors, said main store and said table store; a control unit connected to said data-bus to control the data-bus for access by a selected processor to the table store and the main store and to address a particular table of said table store in accord with the selected processor, to pass the A digits of the addressing word of the selected processor to said particular table and thereby address a particular codeword of said particular table, and to pass the Z digits of said particular codeword, together with the B digits of said addressing word of the selected processor to address a particular storage area of said main store whereby to expand the address capability of the selected processor by the value 2.sup.(Z+B) -2.sup.(A+B).