Data transfer using bus address lines

Claim 1

A system for transferring data in a digital computer, comprising: a bus having address lines, data lines, and control liens; a master subsystem connected to said bus; a slave subsystem connected to said bus; a control line in said bus for communicating a transfer mode signal, wherein data is transferred between said master subsystem and said slave subsystem on the data lines when the transfer mode signal indicates a first mode, and wherein data is transferred between said master subsystem and said slave subsystem on the data lines and on at least one of the address lines when the transfer mode signal indicates a second mode; a clock line in said bus for communicating a clock signal; a high speed line in said bus for communicating a high speed clock signal, wherein data is transferred under the control of the high speed clock signal when the transfer mode signal indicates the second mode; a transfer rate line in said bus for communicating a transfer rate signal, wherein the high speed clock signal operates at a rate determined by the transfer rate signal when the transfer mode signal indicates the second transfer mode; and a ready line in said bus for communicating a ready signal under control of said slave subsystem, wherein data is transferred under the control of the high speed clock when the ready signal indicates that said slave subsystem is ready to transfer data, and wherein data transfer is suspended when the ready signal indicates that said slave subsystem is not ready to transfer data.

Claim 2

A system for transferring data in a digital computer, comprising: a bus having address lines, data lines, and control liens; a master subsystem connected to said bus; a slave subsystem connected to said bus; a control line in said bus for communicating a transfer mode signal, wherein data is transferred between said master subsystem and said slave subsystem on the data lines when the transfer mode signal indicates a first mode, and wherein data is transferred between said master subsystem and said slave subsystem on the data lines and on at least one of the address lines when the transfer mode signal indicates a second mode; a clock line in said bus for communicating a clock signal; a high speed line in said bus for communicating a high speed clock signal, wherein data is transferred under the control of the high speed clock signal when the transfer mode signal indicates the second mode; a transfer rate line in said bus for communicating a transfer rate signal, wherein the high speed clock signal operates at a rate determined by the transfer rate signal when the transfer mode signal indicates the second transfer mode; and a ready line in said bus for communicating a ready signal under control of said slave subsystem, wherein data is transferred under the control of the high speed clock when the ready signal indicates that said slave subsystem is ready to transfer data, and wherein data transfer is suspended when the ready signal indicates that said slave subsystem is not ready to transfer data.