Patent US5270981A successfully refreshed from Google Patents.
US5270981A
Expired / Lapsed
US
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Field memory device functioning as a variable stage shift register with gated feedback from its output to its input
Assignee: Toshiba Corp
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Filing: 1991-03-04
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Granted: 1993-12-14
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Expires: 2011-03-04
Abstract
Abstract A memory device having an addressing unit for addressing different values as addresses for input/output of data for each clock input during one cycle, and a memory inputting data at different designated addresses and cyclically outputting stored data. The memory device provides the operation of a shift register which is capable of determining the number of stages in accordance with the content of the addressing. By employing a memory which effects read-modify-write operations and by delivering input data obtained by the feedback of output data to this memory, the memory device can repeatedly output the same data. The memory device has a switch circuit operative in a first position for connecting an output of the memory to an input of the memory and in a second position for connecting the input of the memory to an external data source.
Inventors
- 👤 Masahiko Sumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:49
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F5/00; G06F5/06; G06F5/16; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
277 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the same time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, and said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at said different addresses corresponding to said fixed sequence of address signals and to said output of said memory means, said addressing means having a presettable counter which holds an initial value indicative of said predetermined number N of address signals generated by said addressing means and outputting the value successively changing the value by one, and wherein said presettable counter is connected to a shift register which stores said initial value of the presettable counter.
Claim 2
Dependent Claim
277 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the same time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, and said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at said different addresses corresponding to said fixed sequence of address signals and to said output of said memory means, said addressing means having a presettable counter which holds an initial value indicative of said predetermined number N of address signals generated by said addressing means and outputting the value successively changing the value by one, and wherein said presettable counter is connected to a shift register which stores said initial value of the presettable counter.
Claim 3
Dependent Claim
25 words
A memory device as set forth in claim 1, wherein said switch means comprises a gate circuit which operates in response to a switching signal.
Claim 4
Dependent Claim
278 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the same time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at said different addresses corresponding to said fixed sequence of address signals and to said output of said memory means, said addressing means having a presettable counter which holds an initial value indicative of said predetermined number N of address signals generated by said addressing means and outputting the value successively changing the value by one, and wherein said presettable counter is connected to a read only memory device which stores said initial value of the presettable counter.
Claim 5
Dependent Claim
278 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the same time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at said different addresses corresponding to said fixed sequence of address signals and to said output of said memory means, said addressing means having a presettable counter which holds an initial value indicative of said predetermined number N of address signals generated by said addressing means and outputting the value successively changing the value by one, and wherein said presettable counter is connected to a read only memory device which stores said initial value of the presettable counter.
Claim 6
Dependent Claim
25 words
A memory device as set forth in claim 3, wherein said switch means comprises a gate circuit which operates in response to a switching signal.
Claim 7
Dependent Claim
238 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at aid different addresses corresponding to said fixed sequence of address signals and to sand output of said memory means, said addressing means having a random number generator circuit which outputs randomly arranged different values in said fixed sequence.
Claim 8
Dependent Claim
238 words
A memory device comprising: a) addressing means for cyclically generating a predetermined number N of address signals in a fixed sequence during an operating cycle of said memory device and for repetitively generating the same fixed sequence of address signals during successive operating cycles; b) memory means for storing a plurality of bits, said memory means cyclically outputting data stored at different addresses corresponding to said fixed sequence of address signals, and at the time, cyclically writing new data for a next cycle at the same addresses corresponding to said fixed sequence of address signals; and c) switch means operative in a first position for connecting an output of said memory means to an input of said memory means and in a second position for connecting said input of said memory means to an external data source, wherein said memory device is operative with said switch means in said first position for repetitively circulating the same data through said memory means at said different addresses corresponding to said fixed sequence of address signals, said memory device is operative with said switch means in said second position for passing data only from said external data source through said memory means at aid different addresses corresponding to said fixed sequence of address signals and to sand output of said memory means, said addressing means having a random number generator circuit which outputs randomly arranged different values in said fixed sequence.
Claim 9
Dependent Claim
25 words
A memory device as set forth in claim 5, wherein said switch means comprises a gate circuit which operates in response to a switching signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |