US4787065A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions
Assignee: Philips Communication Entreprise
•
Filing: 1988-02-03
•
Granted: 1988-11-22
•
Expires: 2008-02-03
Abstract
Abstract A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented. Such operation is particularly useful for preforming the functions of a fixed or adaptive transversal filter for data transmission, the data stored in the memory being the filter coefficients.
Inventors
- 👤 Bahman Barazesh
- 👤 Luc Mary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:12
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/3552; G06F12/00; G06F12/02; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
319 words
A data processing apparatus comprising: a random access memory for storing data in a plurality of addresses therein; an address register for storing and accessing any address in said memory; an incrementation circuit connected to said address register for selectively incrementing or decrementing the address stored therein; a first auxiliary register for storing a minimum address value; a second auxiliary register for storing a maximum address value; address comparison means having a first input connected to said address register, a second input selectively connectable to either of said first and second auxiliary registers, and an output at which an equality signal is produced when an address signal at the first input matches an address signal at the second input; and address cycling means for controlling the cyclic accessing of successive addresses in said memory in opposite directions between said minimum and maximum address values, such address cycling means having first and second operating states such that: (i) in said first operating state said address cycling means actuates said incrementation circuit to increment the address in said address register; connects the second auxiliary register to said second input of said address comparison means; and, in response to an equality signal produced at the output of said address comparison means, connects the first auxiliary register to said address register to load said minimum address value therein; and (ii) in said second operating state said address cycling means actuates said incrementation circuit to decrement the address in said address register; connects the first auxiliary register to said second input of said address comparison means; and, in response to an equality signal produced at the output of said address comparison means, connects the second auxiliary register to said address register to load said maximum address value therein; whereby the data in said random access memory at addresses therein between said minimum and maximum address values may be cyclically accessed in selectively opposite directions.
Claim 2
Dependent Claim
319 words
A data processing apparatus comprising: a random access memory for storing data in a plurality of addresses therein; an address register for storing and accessing any address in said memory; an incrementation circuit connected to said address register for selectively incrementing or decrementing the address stored therein; a first auxiliary register for storing a minimum address value; a second auxiliary register for storing a maximum address value; address comparison means having a first input connected to said address register, a second input selectively connectable to either of said first and second auxiliary registers, and an output at which an equality signal is produced when an address signal at the first input matches an address signal at the second input; and address cycling means for controlling the cyclic accessing of successive addresses in said memory in opposite directions between said minimum and maximum address values, such address cycling means having first and second operating states such that: (i) in said first operating state said address cycling means actuates said incrementation circuit to increment the address in said address register; connects the second auxiliary register to said second input of said address comparison means; and, in response to an equality signal produced at the output of said address comparison means, connects the first auxiliary register to said address register to load said minimum address value therein; and (ii) in said second operating state said address cycling means actuates said incrementation circuit to decrement the address in said address register; connects the first auxiliary register to said second input of said address comparison means; and, in response to an equality signal produced at the output of said address comparison means, connects the second auxiliary register to said address register to load said maximum address value therein; whereby the data in said random access memory at addresses therein between said minimum and maximum address values may be cyclically accessed in selectively opposite directions.
Claim 3
Dependent Claim
58 words
A data processing apparatus as claimed in claim 1, in combination with a microprocessor system comprising an instruction bus, a data bus and a memory; such apparatus further comprising a circuit for loading said auxiliary registers in response to instruction received from the instruction bus and for loading said principal register with data received from the data bus.
Claim 4
Dependent Claim
41 words
A data processing apparatus as claimed in claim 2, further comprising connection means between an input of the principal register and the data bus in order to store the content of the principal register in the memory of the microprocessor system.
References Cited (Backward Citations)
US3141151A
Cited
US4016543A
Cited
US4241416A
Cited
JPS5733688B2
Cited
US4280199A
Cited
JPS57114950A
Cited
US4422175A
Cited
US4638457A
Cited
US4462074A
Cited
US4628532A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-22 | 1992-05-23 | 1992-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-22 | 1996-05-23 | 1996-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-22 | 2000-05-23 | 2000-11-22 | $7700.00 | Window Closed / Lapsed |