US4481608A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reentrant asynchronous FIFO
Assignee: Varian Inc
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Filing: 1982-03-01
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Granted: 1984-11-06
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Expires: 2002-03-01
Abstract
Abstract Cyclic instrument control and data acquisition functions which are critically dependent upon synchrony are directed from a computer based system including a FIFO buffer adapted to feedback the most recently active word from its output register and re-store said word at a corresponding sequential position in the FIFO queue. To accommodate complex and interleaved control and data acquisition cycles, each FIFO word has a state portion for commanding external devices, a persistence portion for specifying the duration of a selected state active in the FIFO output buffer for a desired persistence interval, and a repetition portion for specifying the number of consecutive discrete repetitions of the currently active state-persistence datum at the output of the FIFO. Termination of the cyclic sequence is accomplished at the expiration of a preselected number of complete repetitions of the cyclic sequence. The FIFO input address is selected automatically in accord with the number of words comprising a single complete sequence of instrument control/data acquisition functions.
Inventors
- 👤 Edward H. Berkowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:28
CPC Classifications
G; G01; G01N; G01N24/00; G01N24/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
157 words
In a sequence buffer comprising an input register, an output register, and a plurality of intermediate registers disposed sequentially between said input register and said output register, each said register adapted to hold a digital word, each said digital word comprising a plurality of bits, means for normally concurrently transferring the content of each said input and intermediate register to registers adjacent thereto in discrete steps toward and into said output register, the improvement comprising: feedback means communicating with said output register for returning each said digital word transferred thereinto to said input register whereby the sequence of digital words defined by the initial content of said sequence buffer is preserved and said transferring is controlably cycled through said sequence buffer; and persistence control means responsive to a persistence portion of the digital word transferred to said output register for retaining the content of said output buffer for an interval of time determined by said persistence portion.
Claim 2
Dependent Claim
157 words
In a sequence buffer comprising an input register, an output register, and a plurality of intermediate registers disposed sequentially between said input register and said output register, each said register adapted to hold a digital word, each said digital word comprising a plurality of bits, means for normally concurrently transferring the content of each said input and intermediate register to registers adjacent thereto in discrete steps toward and into said output register, the improvement comprising: feedback means communicating with said output register for returning each said digital word transferred thereinto to said input register whereby the sequence of digital words defined by the initial content of said sequence buffer is preserved and said transferring is controlably cycled through said sequence buffer; and persistence control means responsive to a persistence portion of the digital word transferred to said output register for retaining the content of said output buffer for an interval of time determined by said persistence portion.
Claim 3
Dependent Claim
53 words
The sequence buffer of claim 1 comprising sequence counter means for counting the number of times the complete sequential content of said sequence buffer has been transferred into said output register and returned to said input register and means for halting the cycling of said sequence buffer after a predetermined number of times.
Claim 4
Dependent Claim
64 words
The sequence buffer of claim 1 wherein each said digital word additionally comprises a repetition portion and said sequence buffer included repetition control means responsive to said repetition portion of each said digital word for retaining said digital word in the output register for a further interval of time by again activating the persistence control means to initiate the specified persistence interval of time.
Claim 5
Dependent Claim
157 words
A sequence buffer comprising an input register, an output register and a plurality of intermediate registers disposed sequentially between said input register and said output register, each said register adapted to hold a specific word in a sequence of digital words each said digital word comprising a plurality of bits apportioned between a data sub-field in a first portion of said bits and a repetition sub-field in a remaining portion of said bits, means connected to each of said registers in said sequence buffer for normally concurrently transferring the content of each input and intermediate register to said registers adjacent thereto to discrete steps toward and into said output register, repetition control means which is activated by said repetition portion of the content of each said digital word for inhibiting said step transferring and retaining that digital word in the output register for an interval of time in dependence upon the bit content of said repetition portion.
Claim 6
Dependent Claim
157 words
A sequence buffer comprising an input register, an output register and a plurality of intermediate registers disposed sequentially between said input register and said output register, each said register adapted to hold a specific word in a sequence of digital words each said digital word comprising a plurality of bits apportioned between a data sub-field in a first portion of said bits and a repetition sub-field in a remaining portion of said bits, means connected to each of said registers in said sequence buffer for normally concurrently transferring the content of each input and intermediate register to said registers adjacent thereto to discrete steps toward and into said output register, repetition control means which is activated by said repetition portion of the content of each said digital word for inhibiting said step transferring and retaining that digital word in the output register for an interval of time in dependence upon the bit content of said repetition portion.
Claim 7
Dependent Claim
23 words
The sequence buffer of claim 4 including means for selecting the interval of time in response to the content of said repetition portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-06 | 1988-05-07 | 1988-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-06 | 1992-05-07 | 1992-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-06 | 1996-05-07 | 1996-11-06 | $7700.00 | Window Closed / Lapsed |