Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
278 words
A random access memory, comprising a plurality of sub-memories, each having an input terminal, an output terminal and a plurality of cells for volatile information storage which are serially connected between said input and output terminals of each sub-memory, rewrite means connected to the output terminal of each sub-memory for recirculating and rewriting each said sub-memory output, output means coupled to each said sub-memory for receiving at least one rewritten information element per sub-memory when it appears on the output terminal of said sub-memery, selection means for producing a signal for selecting a predetermined sub-memory in order to supply an information element, from said sub-memory and through said output means, to an output of the random access memory, input means having an input which is connected to an input of the random access memory and an output which is connected to inputs of the sub-memories for storing modified information therein, clock pulse generator means for shifting the information elements serially and repeatedly through the sub-memory cells under the control of the clock pulses of the clock pulse generator means, a counter coupled to said clock pulse generator means, at least one further cell for volatile information storage coupled to the output of each sub-memory in order to receive rewritten information therefrom under the control of a counter position of the counter, said counter having a number of counting positions which at least equals the number of cells in each sub-memory, the counter passing through its counting positions under the control of the clock pulses in synchronism with the shifting of the information elements in the sub-memories, and said selection means being connectable to outputs of said further cells.
Claim 2
Dependent Claim
278 words
A random access memory, comprising a plurality of sub-memories, each having an input terminal, an output terminal and a plurality of cells for volatile information storage which are serially connected between said input and output terminals of each sub-memory, rewrite means connected to the output terminal of each sub-memory for recirculating and rewriting each said sub-memory output, output means coupled to each said sub-memory for receiving at least one rewritten information element per sub-memory when it appears on the output terminal of said sub-memery, selection means for producing a signal for selecting a predetermined sub-memory in order to supply an information element, from said sub-memory and through said output means, to an output of the random access memory, input means having an input which is connected to an input of the random access memory and an output which is connected to inputs of the sub-memories for storing modified information therein, clock pulse generator means for shifting the information elements serially and repeatedly through the sub-memory cells under the control of the clock pulses of the clock pulse generator means, a counter coupled to said clock pulse generator means, at least one further cell for volatile information storage coupled to the output of each sub-memory in order to receive rewritten information therefrom under the control of a counter position of the counter, said counter having a number of counting positions which at least equals the number of cells in each sub-memory, the counter passing through its counting positions under the control of the clock pulses in synchronism with the shifting of the information elements in the sub-memories, and said selection means being connectable to outputs of said further cells.
Claim 3
Dependent Claim
106 words
A random access memory as claimed in claim 1, further comprising a second memory, wherein said input means comprises, per sub-memory, at least one second further cell for volatile information storage, having an output which is connected, by a first switch, to an input of the relevant sub-memory, said first switch being interconnected, under the control of a counter position of said second counter which is advanced in synchronism with the shifting of the information elements, while simultaneously interrupting the recirculating coupling by the corresponding rewrite means by a second switch which is connected in series therewith in order to feed a sub-memory with modified information.
Claim 4
Dependent Claim
22 words
A random access memory as claimed in claim 2, wherein a second rewrite means is connected in series with said first switch.
Claim 5
Dependent Claim
63 words
A random access memory as claimed in claim 3, wherein said first and second further cells are embodied in a single cell per sub-memory, further comprising a third switch connected between an output of a sub-memory and an input of the associated further cell, at most one of said first and third switches being conductive simultaneously under the control of a counter position.
Claim 6
Dependent Claim
19 words
A memory as claimed in claim 2, wherein the said first and second counter are embodied a single counter.