US5265259A — Blocks and bits sequence reversing device using b…

Claim 1

Independent Claim 221 words

A bit sequence reversing device for reversing a sequence of data having a plurality of blocks, each said block having a predetermined number of bits, comprising: a block reversing unit for reversing the sequence of at least two of said blocks; and a plurality of bit reversing units, each corresponding to one of said blocks, each of said bit reversing units reversing the sequence of said predetermined number of bits in the corresponding block; wherein said block reversing unit comprises a barrel shift unit, and wherein said barrel shift unit comprises: first and second input latch circuits for receiving said data; a series of left shift registers, connected to said first input latch circuit, for shifting an output of said first input latch circuit to a left direction, a series of right shift registers, connected to said second latch input circuit, for shifting an output of said second input latch circuit to a right direction; a first output control circuit, connected to a post-stage of one of said series left shift registers, for selectively outputting data thereof; and a second output control circuit, connected to another post-stage of one of said series right shift registers, for selectively outputting data thereof, thereby said barrel shift unit generates a logical OR result between the outputs of said first and second output control circuits.

Claim 2

Dependent Claim 221 words

A bit sequence reversing device for reversing a sequence of data having a plurality of blocks, each said block having a predetermined number of bits, comprising: a block reversing unit for reversing the sequence of at least two of said blocks; and a plurality of bit reversing units, each corresponding to one of said blocks, each of said bit reversing units reversing the sequence of said predetermined number of bits in the corresponding block; wherein said block reversing unit comprises a barrel shift unit, and wherein said barrel shift unit comprises: first and second input latch circuits for receiving said data; a series of left shift registers, connected to said first input latch circuit, for shifting an output of said first input latch circuit to a left direction, a series of right shift registers, connected to said second latch input circuit, for shifting an output of said second input latch circuit to a right direction; a first output control circuit, connected to a post-stage of one of said series left shift registers, for selectively outputting data thereof; and a second output control circuit, connected to another post-stage of one of said series right shift registers, for selectively outputting data thereof, thereby said barrel shift unit generates a logical OR result between the outputs of said first and second output control circuits.

Claim 3

Dependent Claim 62 words

A device as set forth in claim 1, wherein each of said bit reversing units comprises: said plurality of input latch circuits for receiving all the predetermined number of bits of the corresponding block; and said plurality of output control circuits, each connected to one of said input latch circuits for reversing all the predetermined number of bits of the corresponding block.

Claim 4

Dependent Claim 243 words

A microprocessor, comprising: bus means (SD) for transmitting a plurality of block data, each including a plurality of bit data; an instruction decoder for decoding instructions; a microprogram control unit for generating a plurality of controlling signals, in accordance with an output signal output from said instruction decoder; an arithmetic logic unit connected to said bus means; a barrel shift unit connected to said bus means, for reversing a sequence of at least two of said block data, in accordance with said controlling signal; wherein said barrel shift unit comprises: first and second input latch circuits for receiving said data; a series of left shift registers, connected to said first input latch circuit, for shifting an output of said first input latch circuit to a left direction; a series of right shift registers, connected to said second latch input circuit, for shifting an output of said second input latch circuit to a right direction; a first output control circuit, connected to a post-stage of one of said series left shift registers, for selectively outputting data thereof; and a second control circuit connected to a another post-stage of one of said series left shift registers, for selectively outputting data thereof, said bit-reversing unit receiving an output signal output from said barrel shift unit, and controlled by said controlling signal, wherein said bit-reversing unit corresponds to one of said data blocks and reverses the sequence of said bits predetermined number of in the corresponding block.

Claim 5

Dependent Claim 243 words

A microprocessor, comprising: bus means (SD) for transmitting a plurality of block data, each including a plurality of bit data; an instruction decoder for decoding instructions; a microprogram control unit for generating a plurality of controlling signals, in accordance with an output signal output from said instruction decoder; an arithmetic logic unit connected to said bus means; a barrel shift unit connected to said bus means, for reversing a sequence of at least two of said block data, in accordance with said controlling signal; wherein said barrel shift unit comprises: first and second input latch circuits for receiving said data; a series of left shift registers, connected to said first input latch circuit, for shifting an output of said first input latch circuit to a left direction; a series of right shift registers, connected to said second latch input circuit, for shifting an output of said second input latch circuit to a right direction; a first output control circuit, connected to a post-stage of one of said series left shift registers, for selectively outputting data thereof; and a second control circuit connected to a another post-stage of one of said series left shift registers, for selectively outputting data thereof, said bit-reversing unit receiving an output signal output from said barrel shift unit, and controlled by said controlling signal, wherein said bit-reversing unit corresponds to one of said data blocks and reverses the sequence of said bits predetermined number of in the corresponding block.

Claim 6

Dependent Claim 77 words

A microprocessor according to claim 3, further comprising: said bit-reversing unit connected to an additional bus means (RD), and a register file connected to said bus means (SD) and said additional bus means (RD), wherein an output terminal of said barrel shift unit is connected to said additional bus means (RD), while said bit-reversing unit reverses the sequence of the data received from said additional bus means and outputs reversed data to said additional bus means (RD).

Claim 7

Dependent Claim 36 words

A microprocessor according to claim 3, wherein said barrel shift unit selectively carries out an operation selected from a one-word reversing operation, a half-word reversing operation, and a non-reversing operation, on basis of said controlling signal.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-11-22	1997-05-24	1997-11-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-11-22	2001-05-24	2001-11-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-11-22	2005-05-24	2005-11-23	$7700.00	Window Closed / Lapsed

Blocks and bits sequence reversing device using barrel shift

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