EP0273637A2
Expired / Lapsed
EP
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Bit pattern conversion system
Assignee: Fujitsu Ltd
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Filing: 1987-12-15
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Granted: —
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Expires: 2007-12-15
Abstract
Abstract A bit pattern conversion system for converting the sequence of a bit pattern between a central processing unit (CPU) and a peripheral circuit (CRTC), including a data bus line (DB) connected between the central processing unit (CPU) and the peripheral circuit (CRTC), and a conversion circuit (B) provided in the peripheral circuit (CRTC) for converting the sequence of the bit pattern from a most significant bit to a least significant bit, and vice versa, in accordance with a conversion signal (S).
Inventors
- 👤 Joji Murakami
- 👤 Syogo Sibazaki
- 👤 Junya Tempaku
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:55
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/06; G06F7/76; G06F7/768; G06F3/00; G06F3/14
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
83 words
A bit pattern conversion system for converting the sequence of a bit pattern between a central processing unit (CPU) and a peripheral circuit (CRTC) comprising: a data bus line (DB) connected between the central processing unit (CPU) and the peripheral circuit (CRTC), and a conversion means (B) provided in the peripheral circuit (CRTC) for converting the sequence of the bit pattern from a most significant bit pattern to a least significant bit pattern, and vice versa, in accordance with a conversion signal (S).
Claim 2
Dependent Claim
83 words
A bit pattern conversion system for converting the sequence of a bit pattern between a central processing unit (CPU) and a peripheral circuit (CRTC) comprising: a data bus line (DB) connected between the central processing unit (CPU) and the peripheral circuit (CRTC), and a conversion means (B) provided in the peripheral circuit (CRTC) for converting the sequence of the bit pattern from a most significant bit pattern to a least significant bit pattern, and vice versa, in accordance with a conversion signal (S).
Claim 3
Dependent Claim
23 words
A bit pattern conversion system as claimed in claim 1, wherein the conversion signal (S) is generated by the central processing unit (CPU).
Claim 4
Dependent Claim
23 words
A bit pattern conversion system as claimed in cliam 1, wherein the conversion signal (S) is generated in the peripheral circuit (CRTC) itself.
Claim 5
Dependent Claim
100 words
A bit pattern conversion system as claimed in any one of the preceding claims, wherein the conversion means (B) comprises a plurality of conversion blocks (B₁ to B₄) corresponding to the number of bits, each of the conversion blocks (B₁ to B₄) comprising, two switching inverters (1, 8) turned ON and OFF by a write signal and a read signal generated from the central processing unit (CPU), four AND gates (3, 4, 5, 6) inputting the conversion signal and each of the bits, and two NOR gates (2, 7) connected between the AND gates and the switching inverters (1, 8).
Claim 6
Dependent Claim
45 words
A bit pattern conversion system as claimed in claim 4, wherein the conversion means (B) is connected to a display memory (RAM) through the data bus line (DB), and a bit pattern inverted by the conversion means (B) is stored in the display memory (RAM).
Claim 7
Dependent Claim
31 words
A bit pattern conversion system as claimed in claim 4 or 5, wherein an output of the conversion blocks is switched in correspondence with a write mode and a read mode.
Claim 8
Dependent Claim
32 words
A bit pattern conversion system as claimed in claim 3, wherein the conversion signal (S) is generated in response to an attribute data added to the data in a display memory (RAM).
Claim 9
Dependent Claim
146 words
A bit pattern conversion system for converting the sequence of a bit pattern between a central processing unit (CPU) and a peripheral circuit (CRTC) comprising: data bus lines (DB) connected between the central processing unit (CPU), the peripheral circuit (CRTC) and a display memory (RAM); a switching circuit (D) for switching the data bus lines (DB) between the central processing unit (CPU) and the display memory (RAM) in response to a control signal (S₀) generated from the central processing unit (CPU); and, a conversion means (B) provided in the peripheral circuit for converting the sequence of the bit pattern received from the display memory (RAM) through the data bus lines (DB) based on a conversion signal (S₁), the conversion signal (S₁) being generated in the peripheral circuit (CRTC) itself based on an attribute data in the display memory which is received by the peripheral circuit (CRTC).
Claim 10
Dependent Claim
146 words
A bit pattern conversion system for converting the sequence of a bit pattern between a central processing unit (CPU) and a peripheral circuit (CRTC) comprising: data bus lines (DB) connected between the central processing unit (CPU), the peripheral circuit (CRTC) and a display memory (RAM); a switching circuit (D) for switching the data bus lines (DB) between the central processing unit (CPU) and the display memory (RAM) in response to a control signal (S₀) generated from the central processing unit (CPU); and, a conversion means (B) provided in the peripheral circuit for converting the sequence of the bit pattern received from the display memory (RAM) through the data bus lines (DB) based on a conversion signal (S₁), the conversion signal (S₁) being generated in the peripheral circuit (CRTC) itself based on an attribute data in the display memory which is received by the peripheral circuit (CRTC).
Claim 11
Dependent Claim
43 words
A bit pattern conversion system as claimed in claim 8, wherein the conversion means (B) converts the sequence of the bit pattern received from the display memory (RAM) from a most significant bit pattern to a least significant bit pattern, and vice versa.
References Cited (Backward Citations)
No citation records indexed.
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