Digital data processing circuit having a bit reverse function

Claim 2

A data processing circuit having a bit reverse function comprising a register storing a data having a plurality of bits, a bit reverse circuit coupled to said register and reversing order of a bit string of the data, and a shifting circuit receiving the reversed data and shifting the reversed data according to an information representing the member of bits to be actually reversed.

Claim 3

A data processing circuit as claimed in claim 1, wherein said bit reverse circuit reverses a full bit string of the data.

Claim 4

A data processing circuit as claimed in claim 1, wherein said bit reverse circuit reverses a fixed part of the data in-said register.

Claim 5

A data processing circuit as claimed in claim 1, wherein said shifting circuit has a plurality of switching transistors arranged in a matrix shape, which are divided into a plurality of group, each group having the same transistors in number.

Claim 6

A data processing circuit comprising a register storing a data having a plurality of bits, a bit reverse circuit coupled to said register and reversing a bit string of the data read out of said register, a plurality of signal lines on which the reversed data is derived, a first circuit having a plurality of input terminals each of which is coupled to said signal lines, respectively, a plurality of output terminals, and a plurality of transistors arranged in a matrix shape and inserted between said input terminals and said output terminals , said plurality of transistors being divided into a plurality of groups, each group having the same transistors in number, and a second circuit which selects one of said plurality of groups and turns the transistors in the selected group on such that the reversed data applied at said input terminals is transferred to the output ends of said first circuit through the transistors of the selected group.

Claim 7

A data processing circuit comprising a register storing a data having a plurality of bits, a bit reverse circuit coupled to said register and reversing a bit string of the data read out of said register, a plurality of signal lines on which the reversed data is derived, a first circuit having a plurality of input terminals each of which is coupled to said signal lines, respectively, a plurality of output terminals, and a plurality of transistors arranged in a matrix shape and inserted between said input terminals and said output terminals , said plurality of transistors being divided into a plurality of groups, each group having the same transistors in number, and a second circuit which selects one of said plurality of groups and turns the transistors in the selected group on such that the reversed data applied at said input terminals is transferred to the output ends of said first circuit through the transistors of the selected group.

Claim 8

A data processing circuit having a bit reverse function comprising a memory storing a plurality of data to be processed according to FFT operation, a first register storing at least one data read out of said memory, a bit reverse circuit reversing a bit string of a data stored in said register, a second register in which the data with the reversed bit string is loaded, a shifting circuit shifting the data of said second register rightwardly or leftwardly according to a shift data, and an arithmetic logic unit through which the shifted data is transferred to said first register.

Claim 9

A data processing circuit having a bit reverse function comprising a memory storing a plurality of data to be processed according to FFT operation, a first register storing at least one data read out of said memory, a bit reverse circuit reversing a bit string of a data stored in said register, a second register in which the data with the reversed bit string is loaded, a shifting circuit shifting the data of said second register rightwardly or leftwardly according to a shift data, and an arithmetic logic unit through which the shifted data is transferred to said first register.