New and improved shifter circuit

Claim 2

An array of shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals, P control input terminals and P output terminals, N, M and P are integers, each of said P output terminals of the M shifter circuits in a group being coupled to one another, respectively, so as to form N x P output terminals of said array.

Claim 3

An array as in Claim 1 wherein each of said shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.

Claim 4

An array as in Claim 2 wherein each of said transistor switching means is an MOSFET.

Claim 5

An array as in Claim 2 wherein each of said transistor switching means is a pair of MOSFETs.

Claim 6

An array as in Claim 2 wherein N is equal to eight, M is equal to four and P is equal to four such that said array is a 128-to-32 shifter.

Claim 7

An array as in Claim 2 wherein N is equal to eight, M is equal to one and P is equal to four.

Claim 8

An array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each barrel shifter circuit has P data input terminals, P control input terminals and P output terminals, N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N x P output terminals of said array, wherein each of said barrel shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control elenent wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.

Claim 9

An array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each barrel shifter circuit has P data input terminals, P control input terminals and P output terminals, N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N x P output terminals of said array, wherein each of said barrel shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control elenent wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.

Claim 10

In a circuit arrangement for Multiplexing bytes of data into various orders of arrangements of the bytes, an array of barrel shifter circuits arranged into N groups of M shifter circuits per group and each barrel shifter circuit is disposed for receiving P data input signals and P control input signals and for providing P output signals on P output terminals, wherein N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N x P output terminals of said array.

Claim 11

In a circuit arrangement for Multiplexing bytes of data into various orders of arrangements of the bytes, an array of barrel shifter circuits arranged into N groups of M shifter circuits per group and each barrel shifter circuit is disposed for receiving P data input signals and P control input signals and for providing P output signals on P output terminals, wherein N, M and P are integers, each of said output terminals of the barrel shifter circuits in a group being coupled to one another, respectively, so as to form N x P output terminals of said array.

Claim 12

An array as in Claim 8 wherein each of said shifter circuits comprises P columns by P rows of transistor switching means, each having an input and an output element and a control element wherein the control element of each switching means in a row is coupled to corresponding ones of the control input terminals, the input element of each of the transistor switching means in a column being coupled to corresponding ones of the data input terminals and the output element of each of the transistor switching means in a row being coupled to respective ones of said output terminals shifted in position as a function of control signals supplied on said control input terminals.

Claim 13

An array as in Claim 9 wherein each of said transistor switching means is an MOSFET.

Claim 14

An array as in Claim 9 wherein each of said transistor switching means is a pair of MOSFETs.

Claim 15

An array as in Claim 9 wherein N is equal to eight, M is equal to four and P is equal to four such that said array is a 128-to-32 shifter.

Claim 16

An array as in Claim 9 wherein N is equal to eight, M is equal to one and P is equal to four.