Barrel shifter using bit reversers and having automatic normalization

Claim 2

A barrel shifter comprising: a first bit reverser stage having a first input for a first plurality of data bits and a first output bus for a second plurality of data bits; said first bit reverser stage selectively, in response to a first control signal, operative to output said first plurality of data bits in reverse order as said second plurality of data bits on said first output bus; a shifting stage having a second input coupled to said first output bus for receiving said second plurality of data bits, and a second output bus for a third plurality of data bits; said shifting stage selectively, in response to a second control signal, operative to shift said second plurality of data bits in a first direction and output as said third plurality of data bits on said second output bus; a second bit reverser stage having a third input coupled to said second output bus for said third plurality of data bits and a third output bus for a fourth plurality of data bits; and said second bit reverser stage selectively, in response to a third control signal, operative to output said third plurality of data bits in reverse order as said fourth plurality of data bits on said third output bus.

Claim 3

The barrel shifter as claimed in claim 1 wherein said shifting stage is comprised of a plurality of parallel shifting segments coupled together in a series fashion.

Claim 4

The barrel shifter as claimed in claim 1 wherein said shifting stage is comprised of multiplexors.

Claim 5

The barrel shifter as claimed in claim 3 wherein said multiplexors are 2 to 1 multiplexors.

Claim 6

The barrel shifter as claimed in claim 1 wherein said firt bit reverser stage is comprised of multiplexors.

Claim 7

The barrel shifter as claimed in claim 1 wherein said second bit reverser stage is comprised of multiplexors.

Claim 8

An automatic normalization circuit having: a multi-stage shifting mechanism comprising at least a first and second shifting stage; said first shifting stage having a first input coupled to a first data bus having a first plurality of data lines, and a first output coupled to a second data bus having a second plurality of data lines; said first shifting stage being coupled to a first control line wherein said first shifting stage selectively performs a shifting operation in response to a first control signal on said first control line; said second shifting stage having a second input coupled to said second data bus; said second shifting stage selectively performs a shifting operation in response to a second control signal; a first OR circuit having inputs coupled to selected ones of data lines of said first data bus wherein said first OR circuit outputs a third control signal in response to data on said selected ones of data lines of said first data bus; a second OR circuit having inputs coupled to selected ones of data lines of said second data bus wherein said second OR circuit outputs a fourth control signal in response to data on said selected ones of data lines of said second data bus; a control circuit coupled to the output of said first OR circuit and in response to said third control signal generating said first control signal to effectuate control of said first shifting stage; and said control circuit being also coupled to the output of said second OR circuit and in response to said fourth control signal generating said second control signal to effectuate control of said second shifting stage.

Claim 9

An automatic normalization circuit having: a multi-stage shifting mechanism comprising at least a first and second shifting stage; said first shifting stage having a first input coupled to a first data bus having a first plurality of data lines, and a first output coupled to a second data bus having a second plurality of data lines; said first shifting stage being coupled to a first control line wherein said first shifting stage selectively performs a shifting operation in response to a first control signal on said first control line; said second shifting stage having a second input coupled to said second data bus; said second shifting stage selectively performs a shifting operation in response to a second control signal; a first OR circuit having inputs coupled to selected ones of data lines of said first data bus wherein said first OR circuit outputs a third control signal in response to data on said selected ones of data lines of said first data bus; a second OR circuit having inputs coupled to selected ones of data lines of said second data bus wherein said second OR circuit outputs a fourth control signal in response to data on said selected ones of data lines of said second data bus; a control circuit coupled to the output of said first OR circuit and in response to said third control signal generating said first control signal to effectuate control of said first shifting stage; and said control circuit being also coupled to the output of said second OR circuit and in response to said fourth control signal generating said second control signal to effectuate control of said second shifting stage.

Claim 10

The automatic normalization circuit as claimed in claim 7 wherein said first and second shifting stages are comprised of multiplexors.

Claim 11

The automatic normalization circuit as claimed in claim 8 wherein said multiplexors are 2 to 1 multiplexors.

Claim 12

The automatic normalization circuit as claimed in claim 7 wherein said control circuit generates an output readable by an external device; said output of said control circuit being representative of the state of said first and second control signals.