Expandable parallel binary shifter/rotator

Claim 2

A parallel shifter having minimum time delay comprising: storage register means for storing a group of bits arranged in increasing weight; a group of OR gates having outputs corresponding to said bits after having been shifted a predetermined direction and number of shift steps; and means for shifting said stored group of bits including, a plurality of AND gates conceptually arranged in a skewed multiplication matrix each representing a cross product of said group of bits multiplied by a binary number representing a power of 2 such power being indicative of the number of shift steps, said multiplication of said group of bits and said binary number forming a final product having a least significant half and a most significant half, each of said AND gates having an output respectively connected to one of said OR gates which has the same relative weight as such AND gate relative to the order of such AND gate in said least significant half of said final product or most significant half of said final product, said AND gates having inputs connected as follows--each AND gate is connected to a register bit which is the multiplicand for the cross product represented by such AND gate, first enabling means responsive to a left shift instruction is connected to AND gate inputs representing cross products corresponding to the least significant half of the final product, second enabling means responsive to a right shift instruction is connected to AND gate inputs representing cross products corresponding to the most significant half of the final product, and third enabling means having a plurality of outputs each respectively corresponding to one of said number of shift steps has each output respectively connected to a group of AND gate inputs representing cross products formed by a common multiplier bit of said binary number.

Claim 3

A shifter as in claim 1 which also serves as a rotator of said group of bits where the same group of said OR gates represent both the most and least significant halves of said final product and including means for concurrently activating said first and second enabling means whereby said most and least significant product halves are merged.

Claim 4

A shifter as in claim 1 where said third enabling means is responsive to shift direction as well as said number of shift steps to activate a predetermined one of said plurality of outputs.

Claim 5

A shifter as in claim 1 including arithmetic shift correction means connected to said OR gates and responsive to said number of shift steps and to said shift direction to insert binary "1"s in OR gates otherwise having vacant outputs due to said shift.

Claim 6

A shifter as in claim 1 where said group of OR gates includes a first portion representing the most significant half of the final product and a second portion representing the least significant half of the final product said AND gate outputs being respectively connected to the corresponding OR gate portion.

Claim 7

An expandable parallel shifter including first, second, third and fourth similar shifting units each of said units receiving a group of input bits and providing a shifted output divided into a most significant bit (MSB) portion and a least significant bit (LSB) portion said expandable parallel shifter receiving a binary input word having MSB and LSB portions, said LSB portion of said input word being coupled to the inputs of said first and third shifting units and said MSB portion to the inputs of said second and fourth shifting units and also including means for making the following interconnections: connecting the MSB output of said first unit and the LSB output of said second unit to the LSB output of said third unit in a wired OR; connecting the MSB output of said third unit and the MSB output of said second unit to the LSB output of said fourth unit in a wired OR; and utilizing the LSB output of said first unit and said wired OR output of said third unit to provide the LSB portion of a desired shifted output and utilizing the MSB output of said fourth unit and said wired OR output of said fourth unit to provide the MSB portion of a desired shifted output.

Claim 8

An expandable parallel shifter including first, second, third and fourth similar shifting units each of said units receiving a group of input bits and providing a shifted output divided into a most significant bit (MSB) portion and a least significant bit (LSB) portion said expandable parallel shifter receiving a binary input word having MSB and LSB portions, said LSB portion of said input word being coupled to the inputs of said first and third shifting units and said MSB portion to the inputs of said second and fourth shifting units and also including means for making the following interconnections: connecting the MSB output of said first unit and the LSB output of said second unit to the LSB output of said third unit in a wired OR; connecting the MSB output of said third unit and the MSB output of said second unit to the LSB output of said fourth unit in a wired OR; and utilizing the LSB output of said first unit and said wired OR output of said third unit to provide the LSB portion of a desired shifted output and utilizing the MSB output of said fourth unit and said wired OR output of said fourth unit to provide the MSB portion of a desired shifted output.

Claim 9

A shifter as in claim 6 where each of said shifting units includes storage register means for storing said group of input bits arranged in increasing weight; a group of OR gates having outputs corresponding to said bits after having been shifted a predetermined direction and number of shift steps; and means for shifting said stored group of bits including, a plurality of AND gates conceptually arranged in a skewed multiplication matrix each representing a cross product of said group of bits multiplied by a binary number representing a power of 2 such power being indicative of the number of shift steps, said multiplication of said group of bits and said binary number forming a final product having a least significant half and a most significant half, each of said AND gates having an output respectively connected to one of said OR gates which has the same relative weight as such AND gate relative to the order of such AND gate in said least significant half of said final product or most significant half of said final product, said AND gates having inputs connected as follows--each AND gate is connected to a register bit which is the multiplicand for the cross product represented by such AND gate, first enabling means responsive to a left shift instruction is connected to AND gate inputs representing cross products corresponding to the least significant half of the final product, second enabling means responsive to a right shift instruction is connected to AND gate inputs representing cross products corresponding to the most significant half of the final product, and third enabling means having a plurality of outputs each respectively corresponding to one of said number of shift steps has each output respectively connected to a group of AND gate inputs representing cross products formed by a common multiplier bit of said binary number.