Floating point addition architecture

Claim 2

In combination: shifter means for performing a floating pooint addition operation comprising alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means including a single digit shifter means for shifting digits within said digital word one place during said operation; said shifter means further including a multiple digit shifter means coupled to said single digit shifter means for shifting digits within said digital word a plurality of places, said multiple digit shifter means being traversed by said digital word no more than one time during said floating point addition operation; and arithmetic means for performing an add function during said floating point addition operation, said arithmetic means being coupled to said shifter means whereby said digital word is not required to pass through said arithmetic means solely to gain access to said multiple digit shifter means.

Claim 3

The combination as recited in claim 1 wherein: said shifter means performs left and right shifts of digits within said digital word.

Claim 4

The combination as recited in claim 1 wherein: said arithmetic means performs said add function on two mantissa digital words during said floating point addition operation.

Claim 5

The combination as recited in claim 1 wherein: said multiple digit shifter means comprises a barrel shifter.

Claim 6

The combination as recited in claim 1 including: a microprogram control means for generating control signals.

Claim 7

The combination as recited in claim 5 wherein: said microprogram control means having said control signals coupled to said shifter means and said arithmetic means, simultaneously enables parallel paths comprising said multiple digit shifter means and said arithmetic means, said control means selecting for storage the outputs from only one of said paths as determined by machine status conditions.

Claim 8

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; and said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter traversed by said digital word no more than once during the execution of said floating point addition operation.

Claim 9

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; and said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter traversed by said digital word no more than once during the execution of said floating point addition operation.

Claim 10

The combination as recited in claim 7 wherein: said single digit right shifter comprises means for performing a single digit right shift or no digit shift.

Claim 11

The combination as recited in claim 7 wherein: said single digit left shifter comprises means for performing a single digit left shift or no digit shift.

Claim 12

The combination as recited in claim 7 wherein: said multiple digit shifter comprises means for shifting digits of said digital word a plurality of places left or right.

Claim 13

The combination as recited in claim 7 wherein: said multiple digit shifter performs said alignment or said normalization function but not both during said floating point addition operation.

Claim 14

The combination as recited in claim 7 wherein: said arithmetic means performs said add function on two mantissa digital words during said floating point addition operation.

Claim 15

The combination as recited in claim 7 wherein: said arithmetic means comprises an arithmetic-logic unit for performing said add function.

Claim 16

The combination as recited in claim 7 wherein: said arithmetic means further comprises means for determining the sign of a digital word resulting from said floating point addition operation.

Claim 17

The combination as recited in claim 7 wherein: said multiple digit shifter comprises a barrel shifter.

Claim 18

The combination as recited in claim 7 including: a microprogram control means for generating control signals.

Claim 19

The combination as recited in claim 16 wherein: said microprogram control means having said control signals coupled to said shifter means and said arithmetic means, simultaneously enables parallel paths comprising said multiple digit shifter and said arithmetic means, said control means selecting for storage the output from only one of said paths as determined by machine status conditions.

Claim 20

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter traversed by said digital word no more than once during the execution of said floating point addition operation; means for providing a first digital word to said arithmetic means representing one of two digital words to be added together; and means for providing a second digital word to said arithmetic means representing a second of two digital words to be added together.

Claim 21

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter traversed by said digital word no more than once during the execution of said floating point addition operation; means for providing a first digital word to said arithmetic means representing one of two digital words to be added together; and means for providing a second digital word to said arithmetic means representing a second of two digital words to be added together.

Claim 22

The combination as recited in claim 18 wherein: said single digit right shifter comprises means for performing a single digit right shift or no digit shift.

Claim 23

The combination as recited in claim 18 wherein: said single digit left shifter comprises means for performing a single digit left shift or no digit shift.

Claim 24

The combination as recited in claim 18 wherein: said multiple digit shifter comprises means for shifting digits of a digital word a plurality of places left and right.

Claim 25

The combination as recited in claim 18 wherein: said multiple digit shifter performs said alignment or said normalization function but not both during said floating point addition operation.

Claim 26

The combination as recited in claim 18 wherein: said arithmetic means performs said add function on two mantissa digital words during said floating point addition operation.

Claim 27

The combination as recited in claim 18 wherein: said arithmetic means comprises an arithmetic-logic unit for performing said add function.

Claim 28

The combination as recited in claim 18 wherein: said arithmetic means further comprises means for determining the sign of a digital word resulting from said floating point addition operation.

Claim 29

The combination as recited in claim 18 wherein: said multiple digit shifter comprises a barrel shifter.

Claim 30

The combination as recited in claim 18 including: a microprogram control means for generating control signals.

Claim 31

The combination as recited in claim 27 wherein: said microprogram control means having said control signals coupled to said shifter means and said arithmetic means simultaneously enables parallel paths comprising said multiple digit shifter and said arithmetic means, said control means selecting for storage the output from only one of said paths as determined by machine status conditions.

Claim 32

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single bit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single bit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; said shifter means further comprising, said right shifter coupled in series with said arithmetic means and a multiple bit shifter, said multiple bit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple bit shifter traversed by said digital word no more than once during the execution of said floating point addition operation; means for providing a first digital word to said arithmetic means representing one of two digital words to be added together; and means for providing a second digital word to said arithmetic means representing a second of two digital words to be added together.

Claim 33

In combination: shifter means for performing a floating point addition operation including alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single bit right shifter; arithmetic means coupled to the output of said right shifter for performing an add function during said floating point addition operation; said shifter means further comprising a single bit left shifter coupled to the output of said arithmetic means, said arithmetic means being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; said shifter means further comprising, said right shifter coupled in series with said arithmetic means and a multiple bit shifter, said multiple bit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple bit shifter traversed by said digital word no more than once during the execution of said floating point addition operation; means for providing a first digital word to said arithmetic means representing one of two digital words to be added together; and means for providing a second digital word to said arithmetic means representing a second of two digital words to be added together.

Claim 34

The combination as recited in claim 29 wherein: said single bit right shifter comprises means for performing a single bit right shift or no bit shift.

Claim 35

The combination as recited in claim 29 wherein: said single bit left shifter comprises means for performing a single bit left shift or no bit shift.

Claim 36

The combination as recited in claim 29 wherein: said multiple bit shifter comprises means for shifting bits of a digital word a plurality of places left or right.

Claim 37

The combination as recited in claim 29 wherein: said multiple bit shifter performs said alignment or said normalization function but not both during said floating point addition operation.

Claim 38

The combination as recited in claim 29 wherein: said arithmetic means performs said add function on two mantissa digital words during said floating point addition operation.

Claim 39

The combination as recited in claim 29 wherein: said arithmetic means comprises an arithmetic-logic unit for performing said add function.

Claim 40

The combination as recited in claim 29 wherein: said arithmetic means further comprises means for determining the sign of a digital word resulting from said floating point addition operation.

Claim 41

The combination as recited in claim 29 wherein: said multiple bit shifter comprises a barrel shifter.

Claim 42

The combination as recited in claim 29 including: a microprogram control means for generating control signals.

Claim 43

The combination as recited in claim 38 wherein: said microprogram control means simultaneously enables parallel paths comprising said multiple bit shifter and said arithmetic means, said control means selecting for storage the output from only one of said paths as determined by machine status conditions.

Claim 44

A digital computer comprising: memory means for storing digital words including data and instructions; arithmetic means for performing arithmetic and logic functions, said arithmetic means including a main arithmetic unit and an exponent arithmetic unit; input-output means for controlling the passage of digital words in and out of said computer; control means coupled to said memory means, said arithmetic means and said input-output means for generating signals to perform computer operations; bus means for interconnecting said memory means, said arithmetic means and said input-output means; said main arithmetic unit including shifter means for performing a floating point addition operation comprising alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means including a single digit shifter means for shifting digits within said digital word one place during said operations; said shifter means further including a multiple digit shifter means coupled to said single digit shifter means for shifting digits within said digital word a plurality of places, said multiple digit shifter means being traversed by said digital word no more than one time during said floating point addition operation; and said main arithmetic unit further including an arithmetic logic unit coupled to said shifter means for performing an add function whereby said digital word is not required to pass through said arithmetic-logic unit solely to gain access to said shifter means.

Claim 45

A digital computer comprising: memory means for storing digital words including data and instructions; arithmetic means for performing arithmetic and logic functions, said arithmetic means including a main arithmetic unit and an exponent arithmetic unit; input-output means for controlling the passage of digital words in and out of said computer; control means coupled to said memory means, said arithmetic means and said input-output means for generating signals to perform computer operations; bus means for interconnecting said memory means, said arithmetic means and said input-output means; said main arithmetic unit including shifter means for performing a floating point addition operation comprising alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means including a single digit shifter means for shifting digits within said digital word one place during said operations; said shifter means further including a multiple digit shifter means coupled to said single digit shifter means for shifting digits within said digital word a plurality of places, said multiple digit shifter means being traversed by said digital word no more than one time during said floating point addition operation; and said main arithmetic unit further including an arithmetic logic unit coupled to said shifter means for performing an add function whereby said digital word is not required to pass through said arithmetic-logic unit solely to gain access to said shifter means.

Claim 46

The combination as recited in claim 40 wherein: said input-output means comprises an input-output bus for transferring digital words to and from said computer.

Claim 47

The combination as recited in claim 40 wherein: said shifter means performs left and right shifts of digits within said digital word.

Claim 48

The combination as recited in claim 40 wherein: said arithmetic-logic unit performs said add function on two mantissa digital words during said floating point addition operation.

Claim 49

The combination as recited in claim 40 wherein: said multiple digit shifter means comprises a barrel shifter.

Claim 50

The combination as recited in claim 40 wherein: said control means comprises a microprogram control means for generating said signals.

Claim 51

The combination as recited in claim 45 wherein: said microprogram control means, having said control signals coupled to said shifter means and said arithmetic means, simultaneously enables parallel paths comprising said multiple digit shifter means and said arithmetic logic unit, said control means selecting for storage the outputs from only one of said paths as determined by machine status conditions.

Claim 52

A digital computer comprising: memory means for storing digital words including data and instructions; arithmetic means for performing arithmetic and logic functions, said arithmetic means including a main arithmetic unit and an exponent arithmetic unit; input-output means for controlling the passage of digital words in and out of said computer; control means coupled to said memory means, said arithmetic means and said input-output means for generating signals to perform computer operations; bus means for interconnecting said memory means, said arithmetic means and said input-output means; said main arithmetic unit including shifter means for performing a floating point addition operation comprising alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; said main arithmetic unit further including an arithmetic-logic unit coupled to the output of said right shifter for performing an add function; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic logic unit, said arithmetic-logic unit being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; and said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter being traversed by said digital word no more than once during the execution of said floating point addition operation.

Claim 53

A digital computer comprising: memory means for storing digital words including data and instructions; arithmetic means for performing arithmetic and logic functions, said arithmetic means including a main arithmetic unit and an exponent arithmetic unit; input-output means for controlling the passage of digital words in and out of said computer; control means coupled to said memory means, said arithmetic means and said input-output means for generating signals to perform computer operations; bus means for interconnecting said memory means, said arithmetic means and said input-output means; said main arithmetic unit including shifter means for performing a floating point addition operation comprising alignment and normalization functions wherein a digital word passes through said shifter means only once to accomplish each of said functions; said shifter means comprising a single digit right shifter; said main arithmetic unit further including an arithmetic-logic unit coupled to the output of said right shifter for performing an add function; said shifter means further comprising a single digit left shifter coupled to the output of said arithmetic logic unit, said arithmetic-logic unit being traversed by a digital word only for performing an arithmetic function and not solely for said digital word to gain access to said shifter means; and said shifter means further comprising, a right shifter coupled in series with said arithmetic means and a multiple digit shifter, said multiple digit shifter being coupled in parallel with said arithmetic means and said left shifter, said multiple digit shifter being traversed by said digital word no more than once during the execution of said floating point addition operation.

Claim 54

The combination as recited in claim 47 wherein: said input-output means comprises an input-output bus for transferring digital words to and from said computer.

Claim 55

The combination as recited in claim 47 wherein: said single digit right shifter comprises means for performing a single digit right shift or no digit shift.

Claim 56

The combination as recited in claim 47 wherein: said single digit left shifter comprises means for performing a single digit left shift or no digit shift.

Claim 57

The combination as recited in claim 47 wherein: said multiple digit shifter comprises means for shifting digits of a digital word a plurality of places left and right.

Claim 58

The combination as recited in claim 47 wherein: said multiple digit shifter performs said alignment or said normalization function but not both during said floating point addition operation.

Claim 59

The combination as recited in claim 47 wherein: said arithmetic logic unit performs said add function on two mantissa digital words during said floating point addition operation.

Claim 60

The combination as recited in claim 47 wherein: said arithmetic means further comprises means for determining the sign of a digital word resulting from said floating point addition operation.

Claim 61

The combination as recited in claim 47 wherein: said multiple digit shifter comprises a barrel shifter.

Claim 62

The combination as recited in claim 47 wherein: said control means comprises a microprogram control means for generating said signals.

Claim 63

The combination as recited in claim 56 wherein: said microprogram control means simultaneously enables parallel paths comprising said multiple digit shifter and said arithmetic means, said control means selecting for storage the output from only one of said paths as determined by machine status conditions.

Claim 66

The method as recited in claim 58 wherein: said steps utilizing said shifting means includes performing left and right shifts.

Claim 67

The method as recited in claim 58 wherein: said steps utilizing said multiple digit shifter means comprises the use of a barrel shifter.

Claim 68

The method as recited in claim 58 wherein: said steps of performing said alignment function, said first normalization function and said second normalization function include using said single digit shifter means having a digit shift mode and a no digit shift mode.

Claim 69

The method as recited in claim 58 wherein: each step of said method includes generating control signals using microprogram control means.

Claim 70

The method as recited in claim 62 wherein: said control signals generated using said microprogram control means simultaneously enable parallel paths comprising said multiple digit shifter means in one parallel path and said arithmetic means in another parallel path, said control means selecting for storage the output from only one of said paths as determined by status conditions of said floating point addition operation.