Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
118 words
A normalize shift count network comprising: means for receiving an unnormalized binary operand including an associated sign bit, a comparison means, connected with said means for receiving said operand, for comparing adjacent binary bits of said operand comprising a plurality of comparison networks, one of said networks comparing the sign bit of said operand with the highest order bit of said operand, each of said networks producing a first type of signal when said compared bits are alike and a second type of signal when said compared bits are different said comparison means producing an output signal indicative of the most significant operand bit, and a logic tree for producing a normalize shift count from said output signal.
Claim 2
Dependent Claim
118 words
A normalize shift count network comprising: means for receiving an unnormalized binary operand including an associated sign bit, a comparison means, connected with said means for receiving said operand, for comparing adjacent binary bits of said operand comprising a plurality of comparison networks, one of said networks comparing the sign bit of said operand with the highest order bit of said operand, each of said networks producing a first type of signal when said compared bits are alike and a second type of signal when said compared bits are different said comparison means producing an output signal indicative of the most significant operand bit, and a logic tree for producing a normalize shift count from said output signal.
Claim 3
Dependent Claim
118 words
A normalize shift count network for producing a shift count for an operand comprising: means for comparing adjacent bits of an operand, said means comprising an operand input receiver and a plurality of comparison networks connected thereto, each of said networks being associated with a bit of said operand and another bit of said operand adjacent thereto, each of said networks producing a first output when compared adjacent bits are alike and a second output when compared adjacent bits are not alike, a logic tree, connected to said means, for producing the bits of the shift count operand dependent on the comparison network having an output indicative of the highest order adjacent operand bits which are not alike.
Claim 4
Dependent Claim
118 words
A normalize shift count network for producing a shift count for an operand comprising: means for comparing adjacent bits of an operand, said means comprising an operand input receiver and a plurality of comparison networks connected thereto, each of said networks being associated with a bit of said operand and another bit of said operand adjacent thereto, each of said networks producing a first output when compared adjacent bits are alike and a second output when compared adjacent bits are not alike, a logic tree, connected to said means, for producing the bits of the shift count operand dependent on the comparison network having an output indicative of the highest order adjacent operand bits which are not alike.
Claim 5
Dependent Claim
15 words
The apparatus of claim 2 in which said comparison networks are Exclusive OR logic elements.
Claim 6
Dependent Claim
194 words
The apparatus of claim 2 wherein said shift count network comprises a first and second section, each of said sections including an associated portion of said means for comparing and an associated portion of said logic tree for producing a shift count operand so that said apparatus may operate on either two one-half conventional width operands simultaneously by means of independent operation of said first and second sections or on one full width operand by means of joint operation of said first and second sections, interconnecting means connected between said first and second sections for operation in the full width mode for providing an input of operand bits to the portions of said comparison means associated with said first and second sections to compare adjacent operand bits dividing the sections and further comprising, means for selecting which of said sections contains the shift count in the full width mode by sensing whether or not the bits in the section associated with the highest ordered operand bits are all alike or not alike, said means for selecting generating an output signal responsive to the logic tree in the section producing the correct shift count operand.