Floating point arithmetic circuit

Claim 1

A CIRCUIT FOR USE WITH A FLOATING-POINT ADDER CIRCUIT, COMPRISING: FIRST N STAGE SHIFTABLE STORAGE REGISTER MEANS RESPONSIVE TO THE ADDER CIRCUIT FOR STORING THE MOST SIGNIFICANT HALF OF THE SUM OF THE MANTISSAS; SECOND N STAGE STORAGE REGISTER MEANS RESPONSIVE TO SAID ADDER CIRCUIT FOR STORING THE LEAST SIGNIFICANT HALF OF SAID SUM; MEANS FOR SENSING THE MOST SIGNIFICANT BIT OF SAID FIRST REGISTER MEANS AND FOR SHIFTING THE CONTENTS OF SAID FIRST REGISTER MEANS A NUMBER OF STAGES UNTIL SAID MOST SIGNIFICANT BIT IS OF A FIRST PREDETERMINED VALUE; MEANS FOR GENERATING A CHARACTERISTIC FOR SAID SUM; FIRST SUBRACTING MEANS RESPONSIVE TO SAID SENSING MEANS FOR SUBTRACTING FROM SAID SUM CHARACTERISTIC THE NUMBER OF STAGES OF SO SHIFTED; THIRD REGISTER MEANS INCLUDING N STAGES FOR STORING THE SHIFTED CONTENTS OF SAID FIRST REGISTER MEANS AND M STAGES FOR STORING SAID FIRST SUBTRACTED CHARACTERISTIC; SECOND SUBSTRACTING MEANS FOR SUBSTRACTING N FROM SAID SUM CHARACTERISTIC; FOURTH STORAGE REGISTER MEANS INCLUDING N STAGES FOR STORING THE CONTENTS OF SAID SECOND REGISTER MEANS AND M STAGES FOR STORING SAID SECOND SUBTRACTED CHARACTERISTIC.