Method of forming a thyristor on an SOI substrate

Claim 1

A method of forming a thyristor, comprising the steps of: forming a semiconductor layer on an insulating layer; forming a first n type region through the semiconductor layer and abutting said insulating layer; forming a first p type region through said semiconductor layer and abutting said insulating layer, said first p type region adjacent said first n type region; forming a second n type region disposed through said semiconductor layer and abutting said insulating layer, said second n type region adjacent said first p type region; forming a second p type region disposed through said semiconductor layer and abutting said insulating layer, said second p type region adjacent said second n type region; forming a third n type region disposed through said semiconductor layer and abutting said insulating layer, said third n type region adjacent said second p type region; forming a third p type region disposed through said semiconductor layer and abutting said insulating layer, said third p type region adjacent said third n type region; and forming a gate overlying portions of said second and third n type regions and said second p type region.

Claim 2

A method of forming a thyristor, comprising the steps of: forming a semiconductor layer on an insulating layer; forming a first n type region through the semiconductor layer and abutting said insulating layer; forming a first p type region through said semiconductor layer and abutting said insulating layer, said first p type region adjacent said first n type region; forming a second n type region disposed through said semiconductor layer and abutting said insulating layer, said second n type region adjacent said first p type region; forming a second p type region disposed through said semiconductor layer and abutting said insulating layer, said second p type region adjacent said second n type region; forming a third n type region disposed through said semiconductor layer and abutting said insulating layer, said third n type region adjacent said second p type region; forming a third p type region disposed through said semiconductor layer and abutting said insulating layer, said third p type region adjacent said third n type region; and forming a gate overlying portions of said second and third n type regions and said second p type region.

Claim 14

A method of forming thyristor structure comprising the steps of: forming a first lateral transistor having base, emitter and collector regions directly on a surface of a first layer; forming a second lateral transistor having base, emitter and collector regions directly on said surface of said first layer, the collector of the first lateral transistor coupled to the base of the second lateral transistor and the base of the first lateral transistor coupled to the collector of the second lateral transistor; and providing decoupling circuitry including a gate electrode coupled between the base of the first transistor and the collector of the second lateral transistor, said decoupling circuitry capable to prevent current flow through the base of the first transistor responsive to a predetermined voltage of the gate electrode.

Claim 15

A method of forming thyristor structure comprising the steps of: forming a first lateral transistor having base, emitter and collector regions directly on a surface of a first layer; forming a second lateral transistor having base, emitter and collector regions directly on said surface of said first layer, the collector of the first lateral transistor coupled to the base of the second lateral transistor and the base of the first lateral transistor coupled to the collector of the second lateral transistor; and providing decoupling circuitry including a gate electrode coupled between the base of the first transistor and the collector of the second lateral transistor, said decoupling circuitry capable to prevent current flow through the base of the first transistor responsive to a predetermined voltage of the gate electrode.