US4631567A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PNPN integrated circuit protective device with integral resistor
Assignee: Fujitsu Ltd
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Filing: 1985-01-23
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Granted: 1986-12-23
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Expires: 2005-01-23
Abstract
Abstract A semiconductor device comprises an internal circuit and an electrostatic destruction preventing circuit connected between a predetermined electrical potential point and a signal input terminal with respect to the internal circuit. The electrostatic destruction preventing circuit comprises a PNP-transistor having its emitter connected to the predetermined electrical potential point, an NPN-transistor having its emitter connected to said signal input terminal and said internal circuit, collector connected to the base of the PNP-transistor, and base connected to the collector of said PNP-transistor, and a resistor connected between the base of the PNP-transistor and the base of the NPN-transistor.
Inventors
- 👤 Masayuki Kokado
- 👤 Hidezi Sumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:25
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0812; H03K17/08126; H10; H10D; H10D84/00; H10D84/60; H10D84/676; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
154 words
A semiconductor device for receiving an input signal, comprising: a substrate, an internal circuit formed in the substrate and an electrostatic destruction preventing circuit formed in the substrate and connected between a predetermined electrical potential point which is operatively connected to receive a most negative power supply voltage, and having a signal input terminal which is operatively connected to receive the input signal for said internal circuit, wherein said electrostatic destruction preventing circuit comprises: a PNP-transistor having a collector region, a base region, and an emitter region connected to said predetermined electrical potential point; an NPN-transistor having an emitter region connected to said signal input terminal and to said internal circuit, a collector region connected to the base region of said PNP-transistor, and a base region connected to the collector region of said PNP-transistor; and resistor means comprising a portion of the collector region of said PNP-transistor, and the base region of said NPN-transistor.
Claim 2
Dependent Claim
154 words
A semiconductor device for receiving an input signal, comprising: a substrate, an internal circuit formed in the substrate and an electrostatic destruction preventing circuit formed in the substrate and connected between a predetermined electrical potential point which is operatively connected to receive a most negative power supply voltage, and having a signal input terminal which is operatively connected to receive the input signal for said internal circuit, wherein said electrostatic destruction preventing circuit comprises: a PNP-transistor having a collector region, a base region, and an emitter region connected to said predetermined electrical potential point; an NPN-transistor having an emitter region connected to said signal input terminal and to said internal circuit, a collector region connected to the base region of said PNP-transistor, and a base region connected to the collector region of said PNP-transistor; and resistor means comprising a portion of the collector region of said PNP-transistor, and the base region of said NPN-transistor.
Claim 3
Dependent Claim
138 words
A semiconductor device as claimed in claim 1, wherein said PNP-transistor comprises: an emitter comprising a P-type substrate operatively connected to receive said most negative power supply voltage, a base region comprising an N-type layer formed in said substrate, and a collector region comprising a P-type region formed in said N-type layer; wherein said NPN-transistor comprises: a collector region comprising said N-type layer, a base region comprising said P-type region, and an emitter region comprising an N-type region formed in said P-type region, said N-type layer forming the base region of said PNP-transistor and said P-type region forming the base region of said NPN-transistor; and said device further includes a wiring layer formed on said substrate such that said P-type region forms a resistance between the base region of said PNP-transistor and the base region of said NPN-transistor.
Claim 4
Dependent Claim
28 words
A semiconductor device as claimed in claim 1, wherein said device has a voltage versus current characteristic having a negative resistance region when said NPN-transistor is being saturated.
Claim 5
Dependent Claim
28 words
A semiconductor device as claimed in claim 2 wherein said N-type layer, said N-type region, said P-type substrate, and said P-type region cooperate to form a vertical PNPN-operation.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-22 | 1990-06-23 | 1990-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-22 | 1994-06-23 | 1994-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-22 | 1998-06-23 | 1998-12-23 | $7700.00 | Window Closed / Lapsed |