US4662957A
Expired / Lapsed
US
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Method of producing a gate turn-off thyristor
Assignee: Mitsubishi Electric Corp
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Filing: 1985-04-22
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Granted: 1987-05-05
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Expires: 2005-04-22
Abstract
Abstract A method of producing a gate turn-off thyristor includes producing a first n type impurity region, a second p type impurity region, a third n type impurity region, and a fourth p type impurity region produced in a semiconductor substrate providing a cathode electrode in contact with the first n type impurity region, providing a gate electrode in contact with the second p type impurity region, and an anode electrode which short-circuits the third and the fourth regions at the second main surface of the semiconductor substrate. Gold is diffused into the third region at a predetermined diffusion temperature thereby shortening the life time of carriers in the substrate.
Inventors
- 👤 Hiroyasu Hagino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:26
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/60; H10D62/00; H10D62/80; H10D62/83; H10D62/834; Y; Y10; Y10S; Y10S438/00; Y10S438/904
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
169 words
A method of producing a gate turn-off thyristor, comprising the steps of: forming a first p type impurity region on a top surface of an n type semiconductor substrate; forming a plurality of second n type impurity regions in said first p type impurity region; selectively forming a plurality of third n type impurity regions on a bottom surface of said semiconductor substrate; forming a plurality of fourth p type impurity regions of said bottom surface on those areas in which said third n type impurity regions are not present; providing a cathode electrode in contact with each of said second n type impurity regions providing a gate electrode in contact with said first p type impurity region; and providing an anode electrode which short-circuits the third and the fourth regions at said bottom surface of the semiconductor substrate, wherein gold is diffused through said third n type regions into said semiconductor substrate at a predetermined diffusion temperature, thereby shortening the life time of carriers present in said substrate.
Claim 2
Independent Claim
169 words
A method of producing a gate turn-off thyristor, comprising the steps of: forming a first p type impurity region on a top surface of an n type semiconductor substrate; forming a plurality of second n type impurity regions in said first p type impurity region; selectively forming a plurality of third n type impurity regions on a bottom surface of said semiconductor substrate; forming a plurality of fourth p type impurity regions of said bottom surface on those areas in which said third n type impurity regions are not present; providing a cathode electrode in contact with each of said second n type impurity regions providing a gate electrode in contact with said first p type impurity region; and providing an anode electrode which short-circuits the third and the fourth regions at said bottom surface of the semiconductor substrate, wherein gold is diffused through said third n type regions into said semiconductor substrate at a predetermined diffusion temperature, thereby shortening the life time of carriers present in said substrate.
Claim 3
Dependent Claim
40 words
A method of producing a gate turn-off thyristor as defined in claim 1, wherein the diffusion temperature is set at 820° C. to 845° C. when producing a gate turn-off thyristor, having a blocking voltage of 1000 to 2000 volts.
Claim 4
Dependent Claim
39 words
A method of producing a gate turn-off thyristor as defined in claim 1, wherein the diffusion temperature is set at 800° to 830° C. when producing a gate turn-off thyristor having a blocking voltage of 2000 to 3000 volts.
Claim 5
Dependent Claim
40 words
A method of producing a gate turn-off thyristor as defined in claim 1, wherein the diffusion temperature is set at 760° to 810° C. when producing a gate turn off thyristor having a blocking voltage of 3000 to 5000 volts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-05-04 | 1990-11-03 | 1991-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-05-04 | 1994-11-03 | 1995-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-05-04 | 1998-11-03 | 1999-05-05 | $7700.00 | Window Closed / Lapsed |