US5237528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory
Assignee: Hitachi Ltd
•
Filing: 1992-01-17
•
Granted: 1993-08-17
•
Expires: 2012-01-17
Abstract
Abstract A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
Inventors
- 👤 Hideo Sunami
- 👤 Tokuo Kure
- 👤 Masanobu Miyao
- 👤 Yoshifumi Kawamoto
- 👤 Katsuhiro Shimohigashi
- 👤 Yoshio Sakai
- 👤 Osamu Minato
- 👤 Toshiaki Masuhara
- 👤 Mitsumasa Koyanagi
- 👤 Shinji Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:37
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/39; H10B12/395; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
165 words
A semiconductor memory comprising: a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor, wherein a source and a drain of said insulated-gate field-effect transistor are formed within a first predetermined semiconductor region of a main surface of a substrate, and wherein said capacitor comprises: a first electrode region formed at a surface of a groove at a second predetermined semiconductor region of said main surface of the substrate; a second electrode region formed within said groove as a data storage portion of said capacitor, said second electrode region being connected to said source or drain of said insulated-gate field-effect transistor; and a first insulating film formed within said groove between said first electrode and said second electrode; wherein said first electrode region is electrically separated from said first predetermined semiconductor region so that a potential of the first electrode region can be controlled independently from potentials of said source and drain of said insulated-gate field-effect transistor.
Claim 2
Dependent Claim
165 words
A semiconductor memory comprising: a plurality of memory cells, each of which memory cells includes an insulated-gate field-effect transistor and a capacitor, wherein a source and a drain of said insulated-gate field-effect transistor are formed within a first predetermined semiconductor region of a main surface of a substrate, and wherein said capacitor comprises: a first electrode region formed at a surface of a groove at a second predetermined semiconductor region of said main surface of the substrate; a second electrode region formed within said groove as a data storage portion of said capacitor, said second electrode region being connected to said source or drain of said insulated-gate field-effect transistor; and a first insulating film formed within said groove between said first electrode and said second electrode; wherein said first electrode region is electrically separated from said first predetermined semiconductor region so that a potential of the first electrode region can be controlled independently from potentials of said source and drain of said insulated-gate field-effect transistor.
Claim 3
Dependent Claim
25 words
A semiconductor memory according to claim 1, wherein said first electrode regions of capacitors of said plurality of memory cells are coupled to each other.
Claim 4
Dependent Claim
31 words
A semiconductor memory according to claim 2, wherein said first electrode regions of capacitors of said plurality of memory cells are coupled to each other at the bottom of said substrate.
Claim 5
Dependent Claim
18 words
A semiconductor memory according to claim 3, wherein said first electrode region is coupled to a predetermined potential.
Claim 6
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises a single layer of SiO 2 .
Claim 7
Dependent Claim
22 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises a single layer of Si 3 N 4 .
Claim 8
Dependent Claim
24 words
A semiconductor memory according to claim 1, wherein said first insulating film comprises composite layer of SiO 2 and Si 3 N 4 .
Claim 9
Dependent Claim
18 words
A semiconductor memory according to claim 1, wherein said first electrode region is coupled to a ground potential.
Claim 10
Dependent Claim
15 words
A semiconductor memory according to claim 1, wherein said second electrode region comprises polycrystalline silicon.
References Cited (Backward Citations)
US3962713A
Cited
US4432006A
Cited
US4327476A
Cited
EP0108390A1
Cited
JPS59191374A
Cited
JPS60140860A
Cited
EP0149799A2
Cited
EP0154871A2
Cited
JPS60239053A
Cited
JPS60245273A
Cited
US4688063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-16 | 1997-02-15 | 1997-08-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-16 | 2001-02-15 | 2001-08-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-16 | 2005-02-15 | 2005-08-17 | $7700.00 | Window Closed / Lapsed |