One-transistor dynamic random-access memory
Abstract
Abstract in a semiconductor memory having memory cells, a groove (17) is formed in a semiconductor substrate (10), and a semiconductor layer (20) is charged into said groove (17) via an insulating film (18) to form a capacitor electrode. The semiconductor layer (20) stretches on the insulating film (11) formed on the semiconductor substrate (10) and comes into contact with the substrate (10) passing through a hole formed in the insulating film (11) thereby to form a base portion of a switching MOS transistor. The source and drain regions (151, 152) of the transistor are formed on said semiconductor layer on the insulating film (11).
Inventors
- 👤 Yuji Yatsuda
- 👤 Hideo Sunami
- 👤 Osamu Minato
- 👤 Masakazu Aoki
- 👤 Katsuaki Takagi
- 👤 Masashi Horiguchi
- 👤 Masao Tamura
Bibliographic Details
Claims Analysis
Total Claims: 5References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.